sunxi: display: Make lcd display clk phase configurable

While running some tests with an Olinuxino-A13-Micro + a 7" Olimex LCD module
I noticed that the screen flickered. This is caused by the lcd display clk
phase reg value being set to 0, where it should be 1 in this setup.

This commit adds a Kconfig option for the lcd display clk phase, so that we
can set it per board. This defaults to 1, because looking at all the fex
files in sunxi-boards, that is by far the most used value.

This commit updated the Ippo and MSI Primo73 tablet defconfigs to override the
default of 1 with 0, as that is the correct value for those tablets, this
keeps the register settings the same as before this commit.

The Olinuxino-A13 defconfigs are not updated, changing the register setting
for these boards from 0 to 1, this is intentional.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

diff --git a/arch/arm/include/asm/arch-sunxi/display.h b/arch/arm/include/asm/arch-sunxi/display.h
index 2ac8a879dfb6feb5dd298c23322c87063b63d858..ff92a10c40122b067a12625c343867809b2b26b6 100644 (file)
--- a/arch/arm/include/asm/arch-sunxi/display.h
+++ b/arch/arm/include/asm/arch-sunxi/display.h
@@ -249,9 +249,7 @@ struct sunxi_tve_reg {
 #define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n)     (((n) * 2) << 16)
 #define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26)
 #define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE      (1 << 31)
-#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE0    (0 << 28)
-#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE60   (1 << 28)
-#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE120  (2 << 28)
+#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x)  ((x) << 28)
 #define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n)     (((n) & 0x1f) << 4)
 #define SUNXI_LCDC_TCON1_CTRL_ENABLE           (1 << 31)
 #define SUNXI_LCDC_TCON1_TIMING_H_BP(n)                (((n) - 1) << 0)

diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 6a4d764b7c9a94eaa4efe0d49f79d2bcbaf23a07..d4d1fa24e7f287d584e80b6e3a5d3190d661b7d4 100644 (file)
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -338,6 +338,13 @@ config VIDEO_LCD_MODE
        This is in drivers/video/videomodes.c: video_get_params() format, e.g.
        x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
 
+config VIDEO_LCD_DCLK_PHASE
+       int "LCD panel display clock phase"
+       depends on VIDEO
+       default 1
+       ---help---
+       Select LCD panel display clock phase shift, range 0-3.
+
 config VIDEO_LCD_POWER
        string "LCD panel power enable pin"
        depends on VIDEO

diff --git a/configs/Ippo_q8h_v1_2_defconfig b/configs/Ippo_q8h_v1_2_defconfig
index 0447b06c2b178bf546917bf72b1eb39d4a94b80f..e68fff0f3266276fcf2542e3b3c1e40eb3dae16f 100644 (file)
--- a/configs/Ippo_q8h_v1_2_defconfig
+++ b/configs/Ippo_q8h_v1_2_defconfig
@@ -2,6 +2,7 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
 CONFIG_FDTFILE="sun8i-a23-ippo-q8h-v1.2.dtb"
 CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:167,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=0
 CONFIG_VIDEO_LCD_POWER="PH7"
 CONFIG_VIDEO_LCD_BL_EN="PH6"
 CONFIG_VIDEO_LCD_BL_PWM="PH0"

diff --git a/configs/Ippo_q8h_v5_defconfig b/configs/Ippo_q8h_v5_defconfig
index 4e82bf93653e371b85d7c8421b150b43b20ee82a..a26fbb6181f6b64e109b7644833141dfe6eb381f 100644 (file)
--- a/configs/Ippo_q8h_v5_defconfig
+++ b/configs/Ippo_q8h_v5_defconfig
@@ -2,6 +2,7 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=5"
 CONFIG_FDTFILE="sun8i-a23-ippo-q8h-v5.dtb"
 CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:87,ri:168,up:31,lo:13,hs:1,vs:1,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=0
 CONFIG_VIDEO_LCD_POWER="PH7"
 CONFIG_VIDEO_LCD_BL_EN="PH6"
 CONFIG_VIDEO_LCD_BL_PWM="PH0"

diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig
index ef1adc5623136c5d0cf3bc654f1d309df6174fc3..d7310533ccf186178244489a4c2d2d26681336c6 100644 (file)
--- a/configs/MSI_Primo73_defconfig
+++ b/configs/MSI_Primo73_defconfig
@@ -2,6 +2,7 @@ CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER"
 CONFIG_FDTFILE="sun7i-a20-primo73.dtb"
 CONFIG_VIDEO_LCD_MODE="x:1024,y:600,depth:18,pclk_khz:60000,le:60,ri:160,up:13,lo:12,hs:100,vs:10,sync:3,vmode:0"
+CONFIG_VIDEO_LCD_DCLK_PHASE=0
 CONFIG_VIDEO_LCD_POWER="PH8"
 CONFIG_VIDEO_LCD_BL_EN="PH7"
 CONFIG_VIDEO_LCD_BL_PWM="PB2"

diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c
index d92dfa88635260560c871c92536209f18e27c194..b2ac6081d79356c0d3da8d3f14e915153d1d8a1a 100644 (file)
--- a/drivers/video/sunxi_display.c
+++ b/drivers/video/sunxi_display.c
@@ -587,12 +587,7 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode)
                       &lcdc->tcon0_frm_ctrl);
        }
 
-#ifdef CONFIG_VIDEO_LCD_IF_PARALLEL
-       val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE0;
-#endif
-#ifdef CONFIG_VIDEO_LCD_IF_LVDS
-       val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE60;
-#endif
+       val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(CONFIG_VIDEO_LCD_DCLK_PHASE);
        if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT))
                val |= SUNXI_LCDC_TCON_HSYNC_MASK;
        if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT))