x86/intel_rdt/mba: Add schemata file support for MBA

Add support to update the MBA bandwidth values for the domains via the
schemata file.

 - Verify that the bandwidth value is valid

 - Round to the next control step depending on the bandwidth granularity of
   the hardware

 - Convert the bandwidth to delay values and write the delay values to
   the corresponding domain PQOS_MSRs.

[ tglx: Massaged changelog ]

Signed-off-by: Vikas Shivappa <vikas.shivappa@linux.intel.com>
Cc: ravi.v.shankar@intel.com
Cc: tony.luck@intel.com
Cc: fenghua.yu@intel.com
Cc: vikas.shivappa@intel.com
Link: http://lkml.kernel.org/r/1491611637-20417-9-git-send-email-vikas.shivappa@linux.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

diff --git a/arch/x86/include/asm/intel_rdt.h b/arch/x86/include/asm/intel_rdt.h
index 4a90057..bd184e1 100644 (file)
--- a/arch/x86/include/asm/intel_rdt.h
+++ b/arch/x86/include/asm/intel_rdt.h
@@ -181,6 +181,7 @@ struct rdt_resource {
 void rdt_get_cache_infofile(struct rdt_resource *r);
 void rdt_get_mba_infofile(struct rdt_resource *r);
 int parse_cbm(char *buf, struct rdt_resource *r, struct rdt_domain *d);
+int parse_bw(char *buf, struct rdt_resource *r,  struct rdt_domain *d);
 
 extern struct mutex rdtgroup_mutex;
 

diff --git a/arch/x86/kernel/cpu/intel_rdt.c b/arch/x86/kernel/cpu/intel_rdt.c
index 1e410ea..731f70a 100644 (file)
--- a/arch/x86/kernel/cpu/intel_rdt.c
+++ b/arch/x86/kernel/cpu/intel_rdt.c
@@ -116,6 +116,8 @@ struct rdt_resource rdt_resources_all[] = {
                .msr_base               = IA32_MBA_THRTL_BASE,
                .msr_update             = mba_wrmsr,
                .cache_level            = 3,
+               .parse_ctrlval          = parse_bw,
+               .format_str             = "%d=%*d",
        },
 };
 

diff --git a/arch/x86/kernel/cpu/intel_rdt_schemata.c b/arch/x86/kernel/cpu/intel_rdt_schemata.c
index c72c9cc..9467a00 100644 (file)
--- a/arch/x86/kernel/cpu/intel_rdt_schemata.c
+++ b/arch/x86/kernel/cpu/intel_rdt_schemata.c
@@ -29,6 +29,49 @@
 #include <asm/intel_rdt.h>
 
 /*
+ * Check whether MBA bandwidth percentage value is correct. The value is
+ * checked against the minimum and max bandwidth values specified by the
+ * hardware. The allocated bandwidth percentage is rounded to the next
+ * control step available on the hardware.
+ */
+static bool bw_validate(char *buf, unsigned long *data, struct rdt_resource *r)
+{
+       unsigned long bw;
+       int ret;
+
+       /*
+        * Only linear delay values is supported for current Intel SKUs.
+        */
+       if (!r->membw.delay_linear)
+               return false;
+
+       ret = kstrtoul(buf, 10, &bw);
+       if (ret)
+               return false;
+
+       if (bw < r->membw.min_bw || bw > r->default_ctrl)
+               return false;
+
+       *data = roundup(bw, (unsigned long)r->membw.bw_gran);
+       return true;
+}
+
+int parse_bw(char *buf, struct rdt_resource *r, struct rdt_domain *d)
+{
+       unsigned long data;
+
+       if (d->have_new_ctrl)
+               return -EINVAL;
+
+       if (!bw_validate(buf, &data, r))
+               return -EINVAL;
+       d->new_ctrl = data;
+       d->have_new_ctrl = true;
+
+       return 0;
+}
+
+/*
  * Check whether a cache bit mask is valid. The SDM says:
  *     Please note that all (and only) contiguous '1' combinations
  *     are allowed (e.g. FFFFH, 0FF0H, 003CH, etc.).