drm/msm/dp: Remove pixel_rate from struct dp_ctrl

This struct member is stored to in the function that calls the function
which uses it. That's possible with a function argument instead of
storing to a struct member. Pass the pixel_rate as an argument instead
to simplify the code. Note that dp_ctrl_link_maintenance() was storing
the pixel_rate but never using it so we just remove the assignment from
there.

Cc: Kuogee Hsieh <quic_khsieh@quicinc.com>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/490772/
Link: https://lore.kernel.org/r/20220623002540.871994-3-swboyd@chromium.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c
index 7c8e74c..22b239b 100644 (file)
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
@@ -1356,25 +1356,7 @@ static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl)
        if (ret)
                DRM_ERROR("Unable to start link clocks. ret=%d\n", ret);
 
-       drm_dbg_dp(ctrl->drm_dev, "link rate=%d pixel_clk=%d\n",
-               ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate);
-
-       return ret;
-}
-
-static int dp_ctrl_enable_stream_clocks(struct dp_ctrl_private *ctrl)
-{
-       int ret = 0;
-
-       dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel",
-                                       ctrl->dp_ctrl.pixel_rate * 1000);
-
-       ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true);
-       if (ret)
-               DRM_ERROR("Unabled to start pixel clocks. ret=%d\n", ret);
-
-       drm_dbg_dp(ctrl->drm_dev, "link rate=%d pixel_clk=%d\n",
-                       ctrl->link->link_params.rate, ctrl->dp_ctrl.pixel_rate);
+       drm_dbg_dp(ctrl->drm_dev, "link rate=%d\n", ctrl->link->link_params.rate);
 
        return ret;
 }
@@ -1518,8 +1500,6 @@ static int dp_ctrl_link_maintenance(struct dp_ctrl_private *ctrl)
        ctrl->link->phy_params.p_level = 0;
        ctrl->link->phy_params.v_level = 0;
 
-       ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
-
        ret = dp_ctrl_setup_main_link(ctrl, &training_step);
        if (ret)
                goto end;
@@ -1589,14 +1569,16 @@ static int dp_ctrl_on_stream_phy_test_report(struct dp_ctrl *dp_ctrl)
 {
        int ret;
        struct dp_ctrl_private *ctrl;
+       unsigned long pixel_rate;
 
        ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
 
-       ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
+       pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
+       dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel", pixel_rate * 1000);
 
-       ret = dp_ctrl_enable_stream_clocks(ctrl);
+       ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true);
        if (ret) {
-               DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret);
+               DRM_ERROR("Unable to start pixel clocks. ret=%d\n", ret);
                return ret;
        }
 
@@ -1705,11 +1687,12 @@ int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl)
 {
        int rc = 0;
        struct dp_ctrl_private *ctrl;
-       u32 rate = 0;
+       u32 rate;
        int link_train_max_retries = 5;
        u32 const phy_cts_pixel_clk_khz = 148500;
        u8 link_status[DP_LINK_STATUS_SIZE];
        unsigned int training_step;
+       unsigned long pixel_rate;
 
        if (!dp_ctrl)
                return -EINVAL;
@@ -1717,25 +1700,24 @@ int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl)
        ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
 
        rate = ctrl->panel->link_info.rate;
+       pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
 
        dp_power_clk_enable(ctrl->power, DP_CORE_PM, true);
 
        if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) {
                drm_dbg_dp(ctrl->drm_dev,
                                "using phy test link parameters\n");
-               if (!ctrl->panel->dp_mode.drm_mode.clock)
-                       ctrl->dp_ctrl.pixel_rate = phy_cts_pixel_clk_khz;
+               if (!pixel_rate)
+                       pixel_rate = phy_cts_pixel_clk_khz;
        } else {
                ctrl->link->link_params.rate = rate;
                ctrl->link->link_params.num_lanes =
                        ctrl->panel->link_info.num_lanes;
-               ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
        }
 
-       drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%d\n",
+       drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n",
                ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes,
-               ctrl->dp_ctrl.pixel_rate);
-
+               pixel_rate);
 
        rc = dp_ctrl_enable_mainlink_clocks(ctrl);
        if (rc)
@@ -1837,6 +1819,7 @@ int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train)
        int ret = 0;
        bool mainlink_ready = false;
        struct dp_ctrl_private *ctrl;
+       unsigned long pixel_rate;
        unsigned long pixel_rate_orig;
 
        if (!dp_ctrl)
@@ -1844,15 +1827,14 @@ int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train)
 
        ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
 
-       ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;
+       pixel_rate = pixel_rate_orig = ctrl->panel->dp_mode.drm_mode.clock;
 
-       pixel_rate_orig = ctrl->dp_ctrl.pixel_rate;
        if (dp_ctrl->wide_bus_en)
-               ctrl->dp_ctrl.pixel_rate >>= 1;
+               pixel_rate >>= 1;
 
-       drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%d\n",
+       drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n",
                ctrl->link->link_params.rate,
-               ctrl->link->link_params.num_lanes, ctrl->dp_ctrl.pixel_rate);
+               ctrl->link->link_params.num_lanes, pixel_rate);
 
        if (!dp_power_clk_status(ctrl->power, DP_CTRL_PM)) { /* link clk is off */
                ret = dp_ctrl_enable_mainlink_clocks(ctrl);
@@ -1862,9 +1844,11 @@ int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train)
                }
        }
 
-       ret = dp_ctrl_enable_stream_clocks(ctrl);
+       dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel", pixel_rate * 1000);
+
+       ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true);
        if (ret) {
-               DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret);
+               DRM_ERROR("Unable to start pixel clocks. ret=%d\n", ret);
                goto end;
        }
 

diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h
index b563e2e..9f29734 100644 (file)
--- a/drivers/gpu/drm/msm/dp/dp_ctrl.h
+++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h
@@ -16,7 +16,6 @@
 struct dp_ctrl {
        bool orientation;
        atomic_t aborted;
-       u32 pixel_rate;
        bool wide_bus_en;
 };