[LoongArch] Define getSetCCResultType for setting vector setCC type

To avoid trigger "No default SetCC type for vectors!" Assertion.

Differential Revision: https://reviews.llvm.org/D135527

diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 2b00bb4..dae4d81 100644 (file)
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -1944,6 +1944,14 @@ bool LoongArchTargetLowering::shouldInsertFencesForAtomic(
   return false;
 }
 
+EVT LoongArchTargetLowering::getSetCCResultType(const DataLayout &DL,
+                                                LLVMContext &Context,
+                                                EVT VT) const {
+  if (!VT.isVector())
+    return getPointerTy(DL);
+  return VT.changeVectorElementTypeToInteger();
+}
+
 bool LoongArchTargetLowering::hasAndNot(SDValue Y) const {
   // TODO: Support vectors.
   return Y.getValueType().isScalarInteger() && !isa<ConstantSDNode>(Y);

diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
index a0b9a8d..37de50f 100644 (file)
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -107,6 +107,9 @@ public:
                                       Value *Mask, Value *ShiftAmt,
                                       AtomicOrdering Ord) const override;
 
+  EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
+                         EVT VT) const override;
+
   bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
                           MachineFunction &MF,
                           unsigned Intrinsic) const override;

diff --git a/llvm/test/CodeGen/LoongArch/get-setcc-result-type.ll b/llvm/test/CodeGen/LoongArch/get-setcc-result-type.ll
new file mode 100644 (file)
index 0000000..34a5102
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/get-setcc-result-type.ll
@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s \
+; RUN:   | FileCheck %s
+
+define void @getSetCCResultType(ptr %p) {
+; CHECK-LABEL: getSetCCResultType:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    ld.wu $a1, $a0, 12
+; CHECK-NEXT:    sltui $a1, $a1, 1
+; CHECK-NEXT:    sub.d $a1, $zero, $a1
+; CHECK-NEXT:    st.w $a1, $a0, 12
+; CHECK-NEXT:    ld.wu $a1, $a0, 8
+; CHECK-NEXT:    sltui $a1, $a1, 1
+; CHECK-NEXT:    sub.d $a1, $zero, $a1
+; CHECK-NEXT:    st.w $a1, $a0, 8
+; CHECK-NEXT:    ld.wu $a1, $a0, 4
+; CHECK-NEXT:    sltui $a1, $a1, 1
+; CHECK-NEXT:    sub.d $a1, $zero, $a1
+; CHECK-NEXT:    st.w $a1, $a0, 4
+; CHECK-NEXT:    ld.wu $a1, $a0, 0
+; CHECK-NEXT:    sltui $a1, $a1, 1
+; CHECK-NEXT:    sub.d $a1, $zero, $a1
+; CHECK-NEXT:    st.w $a1, $a0, 0
+; CHECK-NEXT:    ret
+entry:
+  %0 = load <4 x i32>, ptr %p, align 16
+  %cmp = icmp eq <4 x i32> %0, zeroinitializer
+  %sext = sext <4 x i1> %cmp to <4 x i32>
+  store <4 x i32> %sext, ptr %p, align 16
+  ret void
+}