if (! TARGET_AUTO_LITPOOLS && ! TARGET_CONST16)
{
+ /* Try to emit MOVI + SLLI sequence, that is smaller
+ than L32R + literal. */
+ if (optimize_size && mode == SImode && register_operand (dst, mode))
+ {
+ HOST_WIDE_INT srcval = INTVAL (src);
+ int shift = ctz_hwi (srcval);
+
+ if (xtensa_simm12b (srcval >> shift))
+ {
+ emit_move_insn (dst, GEN_INT (srcval >> shift));
+ emit_insn (gen_ashlsi3_internal (dst, dst, GEN_INT (shift)));
+ return 1;
+ }
+ }
+
src = force_const_mem (SImode, src);
operands[1] = src;
}
(match_operand:DI 1 "general_operand" ""))]
""
{
- if (CONSTANT_P (operands[1]) && !TARGET_CONST16)
- operands[1] = force_const_mem (DImode, operands[1]);
+ if (CONSTANT_P (operands[1]))
+ {
+ /* Split in halves if 64-bit Const-to-Reg moves
+ because of offering further optimization opportunities. */
+ if (register_operand (operands[0], DImode))
+ {
+ rtx first, second;
+
+ split_double (operands[1], &first, &second);
+ emit_insn (gen_movsi (gen_lowpart (SImode, operands[0]), first));
+ emit_insn (gen_movsi (gen_highpart (SImode, operands[0]), second));
+ DONE;
+ }
+
+ if (!TARGET_CONST16)
+ operands[1] = force_const_mem (DImode, operands[1]);
+ }
if (!register_operand (operands[0], DImode)
&& !register_operand (operands[1], DImode))