}
static bool isDGEMM(unsigned Opcode) {
- return Opcode == AMDGPU::V_MFMA_F64_4X4X4F64_e64 ||
- Opcode == AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64 ||
- Opcode == AMDGPU::V_MFMA_F64_16X16X4F64_e64 ||
- Opcode == AMDGPU::V_MFMA_F64_16X16X4F64_vgprcd_e64 ||
- Opcode == AMDGPU::V_MFMA_F64_16X16X4F64_mac_e64 ||
- Opcode == AMDGPU::V_MFMA_F64_16X16X4F64_mac_vgprcd_e64;
+ return AMDGPU::getMAIIsDGEMM(Opcode);
}
static bool isXDL(const GCNSubtarget &ST, const MachineInstr &MI) {
return Info ? Info->IsSingle : false;
}
+bool getMAIIsDGEMM(unsigned Opc) {
+ const MAIInstInfo *Info = getMAIInstInfoHelper(Opc);
+ return Info ? Info->is_dgemm : false;
+}
+
bool getMAIIsGFX940XDL(unsigned Opc) {
const MAIInstInfo *Info = getMAIInstInfoHelper(Opc);
return Info ? Info->is_gfx940_xdl : false;
struct MAIInstInfo {
uint16_t Opcode;
+ bool is_dgemm;
bool is_gfx940_xdl;
};
LLVM_READONLY
bool getVOP3IsSingle(unsigned Opc);
+/// Returns true if MAI operation is a double precision GEMM.
+LLVM_READONLY
+bool getMAIIsDGEMM(unsigned Opc);
+
LLVM_READONLY
bool getMAIIsGFX940XDL(unsigned Opc);
class MAIInst<string OpName, VOPProfile P, SDPatternOperator node>
: VOP3InstBase<OpName, P, node> {
Instruction Opcode = !cast<Instruction>(NAME);
+ bit is_dgemm = 0;
bit is_gfx940_xdl = 0;
}
defm V_MFMA_F32_16X16X16BF16_1K : MAIInst<"v_mfma_f32_16x16x16bf16_1k", "F32_V4I16_X4", int_amdgcn_mfma_f32_16x16x16bf16_1k>;
}
+ let is_dgemm = 1 in {
defm V_MFMA_F64_16X16X4F64 : MAIInst<"v_mfma_f64_16x16x4f64", "F64_16X16X4F64", int_amdgcn_mfma_f64_16x16x4f64>;
defm V_MFMA_F64_4X4X4F64 : MAIInst<"v_mfma_f64_4x4x4f64", "F64_4X4X4F64", int_amdgcn_mfma_f64_4x4x4f64>;
+ }
} // End Predicates = [isGFX90APlus]
let Predicates = [isGFX940Plus], is_gfx940_xdl = 1 in {
let FilterClass = "MAIInst";
let CppTypeName = "MAIInstInfo";
let Fields = [
- "Opcode", "is_gfx940_xdl"
+ "Opcode", "is_dgemm", "is_gfx940_xdl"
];
let PrimaryKey = ["Opcode"];