[(set_attr "type" "pop")
(set_attr "mode" "SI")])
-(define_insn "*movsi_xor"
+(define_insn "movsi_xor"
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 1 "const0_operand" "i"))
(clobber (reg:CC 17))]
[(reg 17) (const_int 0)]))
(set (match_operand 3 "q_regs_operand" "")
(zero_extend (match_dup 1)))]
- "peep2_reg_dead_p (3, operands[1])
+ "(peep2_reg_dead_p (3, operands[1])
+ || operands_match_p (operands[1], operands[3]))
&& ! reg_overlap_mentioned_p (operands[3], operands[0])"
- [(set (match_dup 3) (const_int 0))
- (set (match_dup 4) (match_dup 0))
+ [(set (match_dup 4) (match_dup 0))
+ (set (strict_low_part (match_dup 5))
+ (match_dup 2))]
+{
+ operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
+ operands[5] = gen_rtx_REG (QImode, REGNO (operands[3]));
+ if (HAVE_movsi_xor)
+ emit_insn (gen_movsi_xor (operands[3], const0_rtx));
+ else
+ emit_insn (gen_movsi (operands[3], const0_rtx));
+})
+
+;; Similar, but match zero_extendhisi2_and, which adds a clobber.
+
+(define_peephole2
+ [(set (reg 17) (match_operand 0 "" ""))
+ (set (match_operand:QI 1 "register_operand" "")
+ (match_operator:QI 2 "ix86_comparison_operator"
+ [(reg 17) (const_int 0)]))
+ (parallel [(set (match_operand 3 "q_regs_operand" "")
+ (zero_extend (match_dup 1)))
+ (clobber (reg:CC 17))])]
+ "(peep2_reg_dead_p (3, operands[1])
+ || operands_match_p (operands[1], operands[3]))
+ && ! reg_overlap_mentioned_p (operands[3], operands[0])"
+ [(set (match_dup 4) (match_dup 0))
(set (strict_low_part (match_dup 5))
(match_dup 2))]
- "operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
- operands[5] = gen_rtx_REG (QImode, REGNO (operands[3]));")
+{
+ operands[4] = gen_rtx_REG (GET_MODE (operands[0]), 17);
+ operands[5] = gen_rtx_REG (QImode, REGNO (operands[3]));
+ if (HAVE_movsi_xor)
+ emit_insn (gen_movsi_xor (operands[3], const0_rtx));
+ else
+ emit_insn (gen_movsi (operands[3], const0_rtx));
+})
\f
;; Call instructions.