define amdgpu_ps i64 @s_srem_i64(i64 inreg %num, i64 inreg %den) {
; CHECK-LABEL: s_srem_i64:
; CHECK: ; %bb.0:
-; CHECK-NEXT: s_or_b64 s[6:7], s[2:3], s[4:5]
-; CHECK-NEXT: s_mov_b32 s0, 0
-; CHECK-NEXT: s_mov_b32 s1, -1
-; CHECK-NEXT: s_and_b64 s[6:7], s[6:7], s[0:1]
-; CHECK-NEXT: v_cmp_ne_u64_e64 vcc, s[6:7], 0
+; CHECK-NEXT: s_mov_b32 s6, 0
+; CHECK-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5]
+; CHECK-NEXT: s_mov_b32 s7, -1
+; CHECK-NEXT: s_and_b64 s[0:1], s[0:1], s[6:7]
+; CHECK-NEXT: v_cmp_ne_u64_e64 vcc, s[0:1], 0
+; CHECK-NEXT: s_mov_b32 s0, 1
; CHECK-NEXT: s_cbranch_vccz .LBB1_2
; CHECK-NEXT: ; %bb.1:
; CHECK-NEXT: s_ashr_i32 s6, s3, 31
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; CHECK-NEXT: v_xor_b32_e32 v0, s6, v0
; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s6, v0
-; CHECK-NEXT: s_mov_b32 s1, 0
+; CHECK-NEXT: s_mov_b32 s0, 0
; CHECK-NEXT: s_branch .LBB1_3
; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
; CHECK-NEXT: .LBB1_3: ; %Flow
-; CHECK-NEXT: s_xor_b32 s0, s1, -1
+; CHECK-NEXT: s_xor_b32 s0, s0, 1
; CHECK-NEXT: s_and_b32 s0, s0, 1
; CHECK-NEXT: s_cmp_lg_u32 s0, 0
; CHECK-NEXT: s_cbranch_scc1 .LBB1_5
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v4, v0
; CHECK-NEXT: v_mad_u64_u32 v[1:2], s[4:5], 0, v5, v[1:2]
; CHECK-NEXT: v_mov_b32_e32 v3, 0x1000
-; CHECK-NEXT: s_bfe_i32 s6, -1, 0x10000
+; CHECK-NEXT: s_bfe_i32 s6, 1, 0x10000
; CHECK-NEXT: v_subb_u32_e64 v2, s[4:5], v9, v1, vcc
; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v9, v1
+; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; CHECK-NEXT: v_sub_i32_e32 v6, vcc, v0, v3
+; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v3
+; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v6, v3
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5]
; CHECK-NEXT: v_mov_b32_e32 v5, s6
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v2
-; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT: v_cndmask_b32_e64 v4, v5, v4, s[4:5]
-; CHECK-NEXT: v_sub_i32_e32 v5, vcc, v0, v3
-; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000
-; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v5, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
-; CHECK-NEXT: v_mov_b32_e32 v8, s4
+; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; CHECK-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc
-; CHECK-NEXT: v_sub_i32_e32 v3, vcc, v5, v3
+; CHECK-NEXT: v_cndmask_b32_e64 v4, v5, v4, s[4:5]
+; CHECK-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
+; CHECK-NEXT: v_sub_i32_e32 v3, vcc, v6, v3
; CHECK-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v1, vcc
-; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; CHECK-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
+; CHECK-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; CGP-NEXT: s_movk_i32 s7, 0x1000
; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4
-; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000
+; CGP-NEXT: s_bfe_i32 s8, 1, 0x10000
; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; CGP-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
; CGP-NEXT: v_trunc_f32_e32 v6, v5
; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; CGP-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s7, v5, v[1:2]
-; CGP-NEXT: v_mov_b32_e32 v5, 0x1000
+; CGP-NEXT: v_sub_i32_e32 v9, vcc, v10, v0
; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], 0, v8, v[6:7]
-; CGP-NEXT: v_sub_i32_e32 v8, vcc, v10, v0
-; CGP-NEXT: v_subb_u32_e64 v9, s[4:5], v11, v6, vcc
+; CGP-NEXT: v_mov_b32_e32 v5, 0x1000
+; CGP-NEXT: v_cvt_f32_ubyte0_e32 v7, 0
+; CGP-NEXT: v_subb_u32_e64 v10, s[4:5], v11, v6, vcc
; CGP-NEXT: v_sub_i32_e64 v0, s[4:5], v11, v6
-; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v5
+; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v5
; CGP-NEXT: v_cndmask_b32_e64 v1, 0, -1, s[4:5]
; CGP-NEXT: v_mov_b32_e32 v6, s8
-; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v9
-; CGP-NEXT: v_cndmask_b32_e64 v10, v6, v1, s[4:5]
+; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v10
+; CGP-NEXT: v_cndmask_b32_e64 v11, v6, v1, s[4:5]
; CGP-NEXT: v_cvt_f32_u32_e32 v1, 0x1000
-; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0
; CGP-NEXT: v_subbrev_u32_e32 v0, vcc, 0, v0, vcc
-; CGP-NEXT: v_mac_f32_e32 v1, 0x4f800000, v6
+; CGP-NEXT: v_sub_i32_e32 v12, vcc, v9, v5
+; CGP-NEXT: v_mac_f32_e32 v1, 0x4f800000, v7
; CGP-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; CGP-NEXT: v_sub_i32_e32 v11, vcc, v8, v5
-; CGP-NEXT: v_subbrev_u32_e32 v12, vcc, 0, v0, vcc
+; CGP-NEXT: v_subbrev_u32_e32 v13, vcc, 0, v0, vcc
+; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v12, v5
; CGP-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v1
; CGP-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; CGP-NEXT: v_trunc_f32_e32 v6, v1
-; CGP-NEXT: v_mac_f32_e32 v0, 0xcf800000, v6
-; CGP-NEXT: v_cvt_u32_f32_e32 v13, v0
-; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000
-; CGP-NEXT: v_mov_b32_e32 v14, s4
-; CGP-NEXT: v_cvt_u32_f32_e32 v15, v6
-; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s6, v13, 0
-; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v11, v5
-; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
-; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v12
-; CGP-NEXT: v_cndmask_b32_e32 v14, v14, v7, vcc
-; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s6, v15, v[1:2]
-; CGP-NEXT: v_sub_i32_e32 v1, vcc, v11, v5
-; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], -1, v13, v[6:7]
-; CGP-NEXT: v_subbrev_u32_e32 v16, vcc, 0, v12, vcc
-; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
-; CGP-NEXT: v_cndmask_b32_e32 v7, v11, v1, vcc
+; CGP-NEXT: v_trunc_f32_e32 v7, v1
+; CGP-NEXT: v_mac_f32_e32 v0, 0xcf800000, v7
+; CGP-NEXT: v_cvt_u32_f32_e32 v14, v0
+; CGP-NEXT: v_cvt_u32_f32_e32 v15, v7
+; CGP-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v13
+; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s6, v14, 0
+; CGP-NEXT: v_cndmask_b32_e32 v16, v6, v8, vcc
+; CGP-NEXT: v_mad_u64_u32 v[7:8], s[4:5], s6, v15, v[1:2]
+; CGP-NEXT: v_sub_i32_e32 v1, vcc, v12, v5
+; CGP-NEXT: v_mad_u64_u32 v[7:8], s[4:5], -1, v14, v[7:8]
+; CGP-NEXT: v_subbrev_u32_e32 v17, vcc, 0, v13, vcc
+; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
+; CGP-NEXT: v_cndmask_b32_e32 v8, v12, v1, vcc
; CGP-NEXT: v_mul_lo_u32 v1, v15, v0
-; CGP-NEXT: v_mul_lo_u32 v11, v13, v6
-; CGP-NEXT: v_mul_hi_u32 v14, v13, v0
-; CGP-NEXT: v_cndmask_b32_e32 v12, v12, v16, vcc
+; CGP-NEXT: v_mul_lo_u32 v12, v14, v7
+; CGP-NEXT: v_mul_hi_u32 v16, v14, v0
+; CGP-NEXT: v_cndmask_b32_e32 v13, v13, v17, vcc
; CGP-NEXT: v_mul_hi_u32 v0, v15, v0
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v11
-; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v14
+; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v12
+; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v16
; CGP-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CGP-NEXT: v_mul_lo_u32 v14, v15, v6
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v11, v1
-; CGP-NEXT: v_mul_hi_u32 v11, v13, v6
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v14, v0
-; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v11
-; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v11, vcc, v14, v11
-; CGP-NEXT: v_mul_hi_u32 v6, v15, v6
+; CGP-NEXT: v_mul_lo_u32 v16, v15, v7
+; CGP-NEXT: v_add_i32_e32 v1, vcc, v12, v1
+; CGP-NEXT: v_mul_hi_u32 v12, v14, v7
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v16, v0
+; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v12
+; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v12, vcc, v16, v12
+; CGP-NEXT: v_mul_hi_u32 v7, v15, v7
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CGP-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v11, v1
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v6, v1
-; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v0
-; CGP-NEXT: v_addc_u32_e32 v13, vcc, v15, v1, vcc
-; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s6, v11, 0
-; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
-; CGP-NEXT: v_cndmask_b32_e32 v8, v8, v7, vcc
-; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s6, v13, v[1:2]
-; CGP-NEXT: v_xor_b32_e32 v1, v8, v4
-; CGP-NEXT: v_ashrrev_i32_e32 v8, 31, v3
-; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], -1, v11, v[6:7]
-; CGP-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc
+; CGP-NEXT: v_add_i32_e32 v1, vcc, v12, v1
+; CGP-NEXT: v_add_i32_e32 v1, vcc, v7, v1
+; CGP-NEXT: v_add_i32_e32 v12, vcc, v14, v0
+; CGP-NEXT: v_addc_u32_e32 v14, vcc, v15, v1, vcc
+; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s6, v12, 0
+; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
+; CGP-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc
+; CGP-NEXT: v_mad_u64_u32 v[7:8], s[4:5], s6, v14, v[1:2]
+; CGP-NEXT: v_xor_b32_e32 v1, v9, v4
+; CGP-NEXT: v_ashrrev_i32_e32 v9, 31, v3
+; CGP-NEXT: v_mad_u64_u32 v[7:8], s[4:5], -1, v12, v[7:8]
+; CGP-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc
+; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v9
+; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v9, vcc
+; CGP-NEXT: v_xor_b32_e32 v11, v2, v9
+; CGP-NEXT: v_mul_lo_u32 v2, v14, v0
+; CGP-NEXT: v_mul_lo_u32 v8, v12, v7
+; CGP-NEXT: v_xor_b32_e32 v13, v3, v9
+; CGP-NEXT: v_mul_hi_u32 v3, v12, v0
+; CGP-NEXT: v_mul_hi_u32 v0, v14, v0
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v8
-; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc
-; CGP-NEXT: v_xor_b32_e32 v10, v2, v8
-; CGP-NEXT: v_mul_lo_u32 v2, v13, v0
-; CGP-NEXT: v_mul_lo_u32 v7, v11, v6
-; CGP-NEXT: v_xor_b32_e32 v12, v3, v8
-; CGP-NEXT: v_mul_hi_u32 v3, v11, v0
-; CGP-NEXT: v_mul_hi_u32 v0, v13, v0
-; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v7
-; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CGP-NEXT: v_mul_lo_u32 v3, v13, v6
-; CGP-NEXT: v_add_i32_e32 v2, vcc, v7, v2
-; CGP-NEXT: v_mul_hi_u32 v7, v11, v6
+; CGP-NEXT: v_mul_lo_u32 v3, v14, v7
+; CGP-NEXT: v_add_i32_e32 v2, vcc, v8, v2
+; CGP-NEXT: v_mul_hi_u32 v8, v12, v7
; CGP-NEXT: v_add_i32_e32 v0, vcc, v3, v0
; CGP-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v7
-; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v7
-; CGP-NEXT: v_mul_hi_u32 v6, v13, v6
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v8
+; CGP-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v8
+; CGP-NEXT: v_mul_hi_u32 v7, v14, v7
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; CGP-NEXT: v_add_i32_e32 v2, vcc, v6, v2
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v11, v0
-; CGP-NEXT: v_addc_u32_e32 v2, vcc, v13, v2, vcc
-; CGP-NEXT: v_mul_lo_u32 v3, v12, v0
-; CGP-NEXT: v_mul_lo_u32 v6, v10, v2
-; CGP-NEXT: v_mul_hi_u32 v7, v10, v0
-; CGP-NEXT: v_mul_hi_u32 v0, v12, v0
-; CGP-NEXT: v_xor_b32_e32 v9, v9, v4
-; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v6
-; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v2, vcc, v7, v2
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v12, v0
+; CGP-NEXT: v_addc_u32_e32 v2, vcc, v14, v2, vcc
+; CGP-NEXT: v_mul_lo_u32 v3, v13, v0
+; CGP-NEXT: v_mul_lo_u32 v7, v11, v2
+; CGP-NEXT: v_mul_hi_u32 v8, v11, v0
+; CGP-NEXT: v_mul_hi_u32 v0, v13, v0
+; CGP-NEXT: v_xor_b32_e32 v10, v10, v4
; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v7
+; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v8
; CGP-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CGP-NEXT: v_mul_lo_u32 v7, v12, v2
-; CGP-NEXT: v_add_i32_e32 v3, vcc, v6, v3
-; CGP-NEXT: v_mul_hi_u32 v6, v10, v2
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v7, v0
+; CGP-NEXT: v_mul_lo_u32 v8, v13, v2
+; CGP-NEXT: v_add_i32_e32 v3, vcc, v7, v3
+; CGP-NEXT: v_mul_hi_u32 v7, v11, v2
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v8, v0
+; CGP-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v7
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v6
-; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6
-; CGP-NEXT: v_add_i32_e32 v11, vcc, v0, v3
-; CGP-NEXT: v_mul_hi_u32 v7, v12, v2
-; CGP-NEXT: v_mad_u64_u32 v[2:3], s[4:5], s7, v11, 0
+; CGP-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; CGP-NEXT: v_add_i32_e32 v12, vcc, v0, v3
+; CGP-NEXT: v_mul_hi_u32 v8, v13, v2
+; CGP-NEXT: v_mad_u64_u32 v[2:3], s[4:5], s7, v12, 0
; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v6, v0
-; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v0
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v7, v0
+; CGP-NEXT: v_add_i32_e32 v7, vcc, v8, v0
; CGP-NEXT: v_mov_b32_e32 v0, v3
-; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s7, v6, v[0:1]
+; CGP-NEXT: v_mad_u64_u32 v[7:8], s[4:5], s7, v7, v[0:1]
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v1, v4
-; CGP-NEXT: v_subb_u32_e32 v1, vcc, v9, v4, vcc
-; CGP-NEXT: v_mad_u64_u32 v[3:4], s[4:5], 0, v11, v[6:7]
-; CGP-NEXT: v_sub_i32_e32 v2, vcc, v10, v2
-; CGP-NEXT: v_subb_u32_e64 v4, s[4:5], v12, v3, vcc
-; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v12, v3
-; CGP-NEXT: s_bfe_i32 s6, -1, 0x10000
-; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v5
-; CGP-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5]
-; CGP-NEXT: v_mov_b32_e32 v7, s6
-; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
+; CGP-NEXT: v_subb_u32_e32 v1, vcc, v10, v4, vcc
+; CGP-NEXT: v_mad_u64_u32 v[3:4], s[4:5], 0, v12, v[7:8]
+; CGP-NEXT: v_sub_i32_e32 v2, vcc, v11, v2
+; CGP-NEXT: v_subb_u32_e64 v4, s[4:5], v13, v3, vcc
+; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v13, v3
; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; CGP-NEXT: v_cndmask_b32_e64 v6, v7, v6, s[4:5]
-; CGP-NEXT: v_sub_i32_e32 v7, vcc, v2, v5
+; CGP-NEXT: v_sub_i32_e32 v8, vcc, v2, v5
; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000
-; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v7, v5
-; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
-; CGP-NEXT: v_mov_b32_e32 v10, s4
+; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v5
+; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v8, v5
+; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
+; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
+; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
-; CGP-NEXT: v_cndmask_b32_e32 v9, v10, v9, vcc
-; CGP-NEXT: v_sub_i32_e32 v5, vcc, v7, v5
+; CGP-NEXT: v_cndmask_b32_e64 v7, v6, v7, s[4:5]
+; CGP-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc
+; CGP-NEXT: v_sub_i32_e32 v5, vcc, v8, v5
; CGP-NEXT: v_subbrev_u32_e32 v10, vcc, 0, v3, vcc
-; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
-; CGP-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc
-; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
+; CGP-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc
+; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc
+; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
; CGP-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; CGP-NEXT: v_xor_b32_e32 v2, v2, v8
-; CGP-NEXT: v_xor_b32_e32 v3, v3, v8
-; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v8
-; CGP-NEXT: v_subb_u32_e32 v3, vcc, v3, v8, vcc
+; CGP-NEXT: v_xor_b32_e32 v2, v2, v9
+; CGP-NEXT: v_xor_b32_e32 v3, v3, v9
+; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v9
+; CGP-NEXT: v_subb_u32_e32 v3, vcc, v3, v9, vcc
; CGP-NEXT: s_setpc_b64 s[30:31]
%result = srem <2 x i64> %num, <i64 4096, i64 4096>
ret <2 x i64> %result
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v4, v0
; CHECK-NEXT: v_mad_u64_u32 v[1:2], s[4:5], 0, v5, v[1:2]
; CHECK-NEXT: v_mov_b32_e32 v3, 0x12d8fb
-; CHECK-NEXT: s_bfe_i32 s6, -1, 0x10000
+; CHECK-NEXT: s_bfe_i32 s6, 1, 0x10000
; CHECK-NEXT: v_subb_u32_e64 v2, s[4:5], v9, v1, vcc
; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v9, v1
+; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
+; CHECK-NEXT: v_sub_i32_e32 v6, vcc, v0, v3
+; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v3
+; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v6, v3
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5]
; CHECK-NEXT: v_mov_b32_e32 v5, s6
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v2
-; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT: v_cndmask_b32_e64 v4, v5, v4, s[4:5]
-; CHECK-NEXT: v_sub_i32_e32 v5, vcc, v0, v3
-; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT: s_bfe_i32 s4, -1, 0x10000
-; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v5, v3
-; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
-; CHECK-NEXT: v_mov_b32_e32 v8, s4
+; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; CHECK-NEXT: v_cndmask_b32_e32 v6, v8, v6, vcc
-; CHECK-NEXT: v_sub_i32_e32 v3, vcc, v5, v3
+; CHECK-NEXT: v_cndmask_b32_e64 v4, v5, v4, s[4:5]
+; CHECK-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc
+; CHECK-NEXT: v_sub_i32_e32 v3, vcc, v6, v3
; CHECK-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v1, vcc
-; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
-; CHECK-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
+; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
+; CHECK-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; CGP-NEXT: s_mov_b32 s7, 0x12d8fb
; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4
-; CGP-NEXT: s_bfe_i32 s8, -1, 0x10000
+; CGP-NEXT: s_bfe_i32 s8, 1, 0x10000
; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; CGP-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4
; CGP-NEXT: v_trunc_f32_e32 v6, v5
; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v5
; CGP-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s7, v5, v[1:2]
-; CGP-NEXT: v_mov_b32_e32 v5, 0x12d8fb
+; CGP-NEXT: v_sub_i32_e32 v9, vcc, v10, v0
; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], 0, v8, v[6:7]
-; CGP-NEXT: v_sub_i32_e32 v8, vcc, v10, v0
-; CGP-NEXT: v_subb_u32_e64 v9, s[4:5], v11, v6, vcc
+; CGP-NEXT: v_mov_b32_e32 v5, 0x12d8fb
+; CGP-NEXT: v_cvt_f32_ubyte0_e32 v7, 0
+; CGP-NEXT: v_subb_u32_e64 v10, s[4:5], v11, v6, vcc
; CGP-NEXT: v_sub_i32_e64 v0, s[4:5], v11, v6
-; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v5
+; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v9, v5
; CGP-NEXT: v_cndmask_b32_e64 v1, 0, -1, s[4:5]
; CGP-NEXT: v_mov_b32_e32 v6, s8
-; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v9
-; CGP-NEXT: v_cndmask_b32_e64 v10, v6, v1, s[4:5]
+; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v10
+; CGP-NEXT: v_cndmask_b32_e64 v11, v6, v1, s[4:5]
; CGP-NEXT: v_cvt_f32_u32_e32 v1, 0x12d8fb
-; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0
; CGP-NEXT: v_subbrev_u32_e32 v0, vcc, 0, v0, vcc
-; CGP-NEXT: v_mac_f32_e32 v1, 0x4f800000, v6
+; CGP-NEXT: v_sub_i32_e32 v12, vcc, v9, v5
+; CGP-NEXT: v_mac_f32_e32 v1, 0x4f800000, v7
; CGP-NEXT: v_rcp_iflag_f32_e32 v1, v1
-; CGP-NEXT: v_sub_i32_e32 v11, vcc, v8, v5
-; CGP-NEXT: v_subbrev_u32_e32 v12, vcc, 0, v0, vcc
+; CGP-NEXT: v_subbrev_u32_e32 v13, vcc, 0, v0, vcc
+; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v12, v5
; CGP-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v1
; CGP-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0
-; CGP-NEXT: v_trunc_f32_e32 v6, v1
-; CGP-NEXT: v_mac_f32_e32 v0, 0xcf800000, v6
-; CGP-NEXT: v_cvt_u32_f32_e32 v13, v0
-; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000
-; CGP-NEXT: v_mov_b32_e32 v14, s4
-; CGP-NEXT: v_cvt_u32_f32_e32 v15, v6
-; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s6, v13, 0
-; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v11, v5
-; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
-; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v12
-; CGP-NEXT: v_cndmask_b32_e32 v14, v14, v7, vcc
-; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s6, v15, v[1:2]
-; CGP-NEXT: v_sub_i32_e32 v1, vcc, v11, v5
-; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], -1, v13, v[6:7]
-; CGP-NEXT: v_subbrev_u32_e32 v16, vcc, 0, v12, vcc
-; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14
-; CGP-NEXT: v_cndmask_b32_e32 v7, v11, v1, vcc
+; CGP-NEXT: v_trunc_f32_e32 v7, v1
+; CGP-NEXT: v_mac_f32_e32 v0, 0xcf800000, v7
+; CGP-NEXT: v_cvt_u32_f32_e32 v14, v0
+; CGP-NEXT: v_cvt_u32_f32_e32 v15, v7
+; CGP-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
+; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v13
+; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s6, v14, 0
+; CGP-NEXT: v_cndmask_b32_e32 v16, v6, v8, vcc
+; CGP-NEXT: v_mad_u64_u32 v[7:8], s[4:5], s6, v15, v[1:2]
+; CGP-NEXT: v_sub_i32_e32 v1, vcc, v12, v5
+; CGP-NEXT: v_mad_u64_u32 v[7:8], s[4:5], -1, v14, v[7:8]
+; CGP-NEXT: v_subbrev_u32_e32 v17, vcc, 0, v13, vcc
+; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v16
+; CGP-NEXT: v_cndmask_b32_e32 v8, v12, v1, vcc
; CGP-NEXT: v_mul_lo_u32 v1, v15, v0
-; CGP-NEXT: v_mul_lo_u32 v11, v13, v6
-; CGP-NEXT: v_mul_hi_u32 v14, v13, v0
-; CGP-NEXT: v_cndmask_b32_e32 v12, v12, v16, vcc
+; CGP-NEXT: v_mul_lo_u32 v12, v14, v7
+; CGP-NEXT: v_mul_hi_u32 v16, v14, v0
+; CGP-NEXT: v_cndmask_b32_e32 v13, v13, v17, vcc
; CGP-NEXT: v_mul_hi_u32 v0, v15, v0
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v11
-; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v14
+; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v12
+; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v16
; CGP-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CGP-NEXT: v_mul_lo_u32 v14, v15, v6
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v11, v1
-; CGP-NEXT: v_mul_hi_u32 v11, v13, v6
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v14, v0
-; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v11
-; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v11, vcc, v14, v11
-; CGP-NEXT: v_mul_hi_u32 v6, v15, v6
+; CGP-NEXT: v_mul_lo_u32 v16, v15, v7
+; CGP-NEXT: v_add_i32_e32 v1, vcc, v12, v1
+; CGP-NEXT: v_mul_hi_u32 v12, v14, v7
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v16, v0
+; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v12
+; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v12, vcc, v16, v12
+; CGP-NEXT: v_mul_hi_u32 v7, v15, v7
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1
; CGP-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v11, v1
-; CGP-NEXT: v_add_i32_e32 v1, vcc, v6, v1
-; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v0
-; CGP-NEXT: v_addc_u32_e32 v13, vcc, v15, v1, vcc
-; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s6, v11, 0
-; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
-; CGP-NEXT: v_cndmask_b32_e32 v8, v8, v7, vcc
-; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s6, v13, v[1:2]
-; CGP-NEXT: v_xor_b32_e32 v1, v8, v4
-; CGP-NEXT: v_ashrrev_i32_e32 v8, 31, v3
-; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], -1, v11, v[6:7]
-; CGP-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc
+; CGP-NEXT: v_add_i32_e32 v1, vcc, v12, v1
+; CGP-NEXT: v_add_i32_e32 v1, vcc, v7, v1
+; CGP-NEXT: v_add_i32_e32 v12, vcc, v14, v0
+; CGP-NEXT: v_addc_u32_e32 v14, vcc, v15, v1, vcc
+; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], s6, v12, 0
+; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
+; CGP-NEXT: v_cndmask_b32_e32 v9, v9, v8, vcc
+; CGP-NEXT: v_mad_u64_u32 v[7:8], s[4:5], s6, v14, v[1:2]
+; CGP-NEXT: v_xor_b32_e32 v1, v9, v4
+; CGP-NEXT: v_ashrrev_i32_e32 v9, 31, v3
+; CGP-NEXT: v_mad_u64_u32 v[7:8], s[4:5], -1, v12, v[7:8]
+; CGP-NEXT: v_cndmask_b32_e32 v10, v10, v13, vcc
+; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v9
+; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v9, vcc
+; CGP-NEXT: v_xor_b32_e32 v11, v2, v9
+; CGP-NEXT: v_mul_lo_u32 v2, v14, v0
+; CGP-NEXT: v_mul_lo_u32 v8, v12, v7
+; CGP-NEXT: v_xor_b32_e32 v13, v3, v9
+; CGP-NEXT: v_mul_hi_u32 v3, v12, v0
+; CGP-NEXT: v_mul_hi_u32 v0, v14, v0
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v8
-; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc
-; CGP-NEXT: v_xor_b32_e32 v10, v2, v8
-; CGP-NEXT: v_mul_lo_u32 v2, v13, v0
-; CGP-NEXT: v_mul_lo_u32 v7, v11, v6
-; CGP-NEXT: v_xor_b32_e32 v12, v3, v8
-; CGP-NEXT: v_mul_hi_u32 v3, v11, v0
-; CGP-NEXT: v_mul_hi_u32 v0, v13, v0
-; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v7
-; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3
; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; CGP-NEXT: v_mul_lo_u32 v3, v13, v6
-; CGP-NEXT: v_add_i32_e32 v2, vcc, v7, v2
-; CGP-NEXT: v_mul_hi_u32 v7, v11, v6
+; CGP-NEXT: v_mul_lo_u32 v3, v14, v7
+; CGP-NEXT: v_add_i32_e32 v2, vcc, v8, v2
+; CGP-NEXT: v_mul_hi_u32 v8, v12, v7
; CGP-NEXT: v_add_i32_e32 v0, vcc, v3, v0
; CGP-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v7
-; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v7
-; CGP-NEXT: v_mul_hi_u32 v6, v13, v6
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v8
+; CGP-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v8
+; CGP-NEXT: v_mul_hi_u32 v7, v14, v7
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v2, vcc, v3, v2
-; CGP-NEXT: v_add_i32_e32 v2, vcc, v6, v2
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v11, v0
-; CGP-NEXT: v_addc_u32_e32 v2, vcc, v13, v2, vcc
-; CGP-NEXT: v_mul_lo_u32 v3, v12, v0
-; CGP-NEXT: v_mul_lo_u32 v6, v10, v2
-; CGP-NEXT: v_mul_hi_u32 v7, v10, v0
-; CGP-NEXT: v_mul_hi_u32 v0, v12, v0
-; CGP-NEXT: v_xor_b32_e32 v9, v9, v4
-; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v6
-; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v2, vcc, v7, v2
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v12, v0
+; CGP-NEXT: v_addc_u32_e32 v2, vcc, v14, v2, vcc
+; CGP-NEXT: v_mul_lo_u32 v3, v13, v0
+; CGP-NEXT: v_mul_lo_u32 v7, v11, v2
+; CGP-NEXT: v_mul_hi_u32 v8, v11, v0
+; CGP-NEXT: v_mul_hi_u32 v0, v13, v0
+; CGP-NEXT: v_xor_b32_e32 v10, v10, v4
; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v7
+; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v8
; CGP-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
-; CGP-NEXT: v_mul_lo_u32 v7, v12, v2
-; CGP-NEXT: v_add_i32_e32 v3, vcc, v6, v3
-; CGP-NEXT: v_mul_hi_u32 v6, v10, v2
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v7, v0
+; CGP-NEXT: v_mul_lo_u32 v8, v13, v2
+; CGP-NEXT: v_add_i32_e32 v3, vcc, v7, v3
+; CGP-NEXT: v_mul_hi_u32 v7, v11, v2
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v8, v0
+; CGP-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v7
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v6
-; CGP-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v6
-; CGP-NEXT: v_add_i32_e32 v11, vcc, v0, v3
-; CGP-NEXT: v_mul_hi_u32 v7, v12, v2
-; CGP-NEXT: v_mad_u64_u32 v[2:3], s[4:5], s7, v11, 0
+; CGP-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; CGP-NEXT: v_add_i32_e32 v12, vcc, v0, v3
+; CGP-NEXT: v_mul_hi_u32 v8, v13, v2
+; CGP-NEXT: v_mad_u64_u32 v[2:3], s[4:5], s7, v12, 0
; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v0, vcc, v6, v0
-; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v0
+; CGP-NEXT: v_add_i32_e32 v0, vcc, v7, v0
+; CGP-NEXT: v_add_i32_e32 v7, vcc, v8, v0
; CGP-NEXT: v_mov_b32_e32 v0, v3
-; CGP-NEXT: v_mad_u64_u32 v[6:7], s[4:5], s7, v6, v[0:1]
+; CGP-NEXT: v_mad_u64_u32 v[7:8], s[4:5], s7, v7, v[0:1]
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v1, v4
-; CGP-NEXT: v_subb_u32_e32 v1, vcc, v9, v4, vcc
-; CGP-NEXT: v_mad_u64_u32 v[3:4], s[4:5], 0, v11, v[6:7]
-; CGP-NEXT: v_sub_i32_e32 v2, vcc, v10, v2
-; CGP-NEXT: v_subb_u32_e64 v4, s[4:5], v12, v3, vcc
-; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v12, v3
-; CGP-NEXT: s_bfe_i32 s6, -1, 0x10000
-; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v5
-; CGP-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5]
-; CGP-NEXT: v_mov_b32_e32 v7, s6
-; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
+; CGP-NEXT: v_subb_u32_e32 v1, vcc, v10, v4, vcc
+; CGP-NEXT: v_mad_u64_u32 v[3:4], s[4:5], 0, v12, v[7:8]
+; CGP-NEXT: v_sub_i32_e32 v2, vcc, v11, v2
+; CGP-NEXT: v_subb_u32_e64 v4, s[4:5], v13, v3, vcc
+; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v13, v3
; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; CGP-NEXT: v_cndmask_b32_e64 v6, v7, v6, s[4:5]
-; CGP-NEXT: v_sub_i32_e32 v7, vcc, v2, v5
+; CGP-NEXT: v_sub_i32_e32 v8, vcc, v2, v5
; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000
-; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v7, v5
-; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
-; CGP-NEXT: v_mov_b32_e32 v10, s4
+; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v2, v5
+; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v8, v5
+; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
+; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v4
+; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
-; CGP-NEXT: v_cndmask_b32_e32 v9, v10, v9, vcc
-; CGP-NEXT: v_sub_i32_e32 v5, vcc, v7, v5
+; CGP-NEXT: v_cndmask_b32_e64 v7, v6, v7, s[4:5]
+; CGP-NEXT: v_cndmask_b32_e32 v6, v6, v10, vcc
+; CGP-NEXT: v_sub_i32_e32 v5, vcc, v8, v5
; CGP-NEXT: v_subbrev_u32_e32 v10, vcc, 0, v3, vcc
-; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
-; CGP-NEXT: v_cndmask_b32_e32 v5, v7, v5, vcc
-; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
+; CGP-NEXT: v_cndmask_b32_e32 v5, v8, v5, vcc
+; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc
+; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
; CGP-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc
-; CGP-NEXT: v_xor_b32_e32 v2, v2, v8
-; CGP-NEXT: v_xor_b32_e32 v3, v3, v8
-; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v8
-; CGP-NEXT: v_subb_u32_e32 v3, vcc, v3, v8, vcc
+; CGP-NEXT: v_xor_b32_e32 v2, v2, v9
+; CGP-NEXT: v_xor_b32_e32 v3, v3, v9
+; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v9
+; CGP-NEXT: v_subb_u32_e32 v3, vcc, v3, v9, vcc
; CGP-NEXT: s_setpc_b64 s[30:31]
%result = srem <2 x i64> %num, <i64 1235195, i64 1235195>
ret <2 x i64> %result
define amdgpu_ps i64 @s_urem_i64(i64 inreg %num, i64 inreg %den) {
; CHECK-LABEL: s_urem_i64:
; CHECK: ; %bb.0:
+; CHECK-NEXT: s_mov_b32 s4, 1
; CHECK-NEXT: s_or_b64 s[6:7], s[0:1], s[2:3]
-; CHECK-NEXT: s_mov_b32 s4, 0
-; CHECK-NEXT: s_mov_b32 s5, -1
-; CHECK-NEXT: s_and_b64 s[6:7], s[6:7], s[4:5]
+; CHECK-NEXT: s_mov_b32 s8, 0
+; CHECK-NEXT: s_mov_b32 s9, -1
+; CHECK-NEXT: s_and_b64 s[6:7], s[6:7], s[8:9]
; CHECK-NEXT: v_cmp_ne_u64_e64 vcc, s[6:7], 0
; CHECK-NEXT: v_cvt_f32_u32_e32 v2, s2
; CHECK-NEXT: s_cbranch_vccz .LBB1_2
; CHECK-NEXT: v_cndmask_b32_e32 v0, v3, v6, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc
-; CHECK-NEXT: s_mov_b32 s5, 0
+; CHECK-NEXT: s_mov_b32 s4, 0
; CHECK-NEXT: s_branch .LBB1_3
; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: ; implicit-def: $vgpr0_vgpr1
; CHECK-NEXT: .LBB1_3: ; %Flow
-; CHECK-NEXT: s_xor_b32 s1, s5, -1
+; CHECK-NEXT: s_xor_b32 s1, s4, 1
; CHECK-NEXT: s_and_b32 s1, s1, 1
; CHECK-NEXT: s_cmp_lg_u32 s1, 0
; CHECK-NEXT: s_cbranch_scc1 .LBB1_5
; CHECK-NEXT: v_cvt_f32_u32_e32 v3, 0x12d8fb
; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v4, 0
; CHECK-NEXT: s_mov_b32 s5, 0xffed2705
-; CHECK-NEXT: s_bfe_i32 s6, -1, 0x10000
-; CHECK-NEXT: s_bfe_i32 s7, -1, 0x10000
+; CHECK-NEXT: s_bfe_i32 s6, 1, 0x10000
; CHECK-NEXT: v_mac_f32_e32 v3, 0x4f800000, v4
; CHECK-NEXT: v_mov_b32_e32 v4, s6
-; CHECK-NEXT: v_mov_b32_e32 v5, s7
; CHECK-NEXT: v_rcp_iflag_f32_e32 v3, v3
; CHECK-NEXT: v_mul_f32_e32 v3, 0x5f7ffffc, v3
-; CHECK-NEXT: v_mul_f32_e32 v6, 0x2f800000, v3
-; CHECK-NEXT: v_trunc_f32_e32 v6, v6
-; CHECK-NEXT: v_mac_f32_e32 v3, 0xcf800000, v6
-; CHECK-NEXT: v_cvt_u32_f32_e32 v6, v6
+; CHECK-NEXT: v_mul_f32_e32 v5, 0x2f800000, v3
+; CHECK-NEXT: v_trunc_f32_e32 v5, v5
+; CHECK-NEXT: v_mac_f32_e32 v3, 0xcf800000, v5
+; CHECK-NEXT: v_cvt_u32_f32_e32 v5, v5
; CHECK-NEXT: v_cvt_u32_f32_e32 v3, v3
-; CHECK-NEXT: v_mul_lo_u32 v7, v6, s5
-; CHECK-NEXT: v_mul_lo_u32 v8, v3, s5
-; CHECK-NEXT: v_mul_hi_u32 v9, s5, v3
-; CHECK-NEXT: v_sub_i32_e32 v7, vcc, v7, v3
-; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v9
-; CHECK-NEXT: v_mul_lo_u32 v9, v6, v8
-; CHECK-NEXT: v_mul_hi_u32 v10, v3, v8
-; CHECK-NEXT: v_mul_hi_u32 v8, v6, v8
-; CHECK-NEXT: v_mul_lo_u32 v11, v3, v7
-; CHECK-NEXT: v_mul_lo_u32 v12, v6, v7
-; CHECK-NEXT: v_mul_hi_u32 v13, v3, v7
-; CHECK-NEXT: v_mul_hi_u32 v7, v6, v7
-; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v11
-; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v8, vcc, v12, v8
-; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v10
-; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v13
-; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v9, vcc, v11, v9
-; CHECK-NEXT: v_add_i32_e32 v10, vcc, v12, v10
-; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v9
-; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v9, vcc, v10, v9
-; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v9
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v8
-; CHECK-NEXT: v_addc_u32_e32 v6, vcc, v6, v7, vcc
+; CHECK-NEXT: v_mul_lo_u32 v6, v5, s5
; CHECK-NEXT: v_mul_lo_u32 v7, v3, s5
; CHECK-NEXT: v_mul_hi_u32 v8, s5, v3
-; CHECK-NEXT: v_mul_lo_u32 v9, v6, s5
-; CHECK-NEXT: v_mul_lo_u32 v10, v6, v7
-; CHECK-NEXT: v_mul_hi_u32 v11, v3, v7
-; CHECK-NEXT: v_mul_hi_u32 v7, v6, v7
-; CHECK-NEXT: v_sub_i32_e32 v9, vcc, v9, v3
-; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
-; CHECK-NEXT: v_mul_lo_u32 v9, v3, v8
-; CHECK-NEXT: v_mul_lo_u32 v12, v6, v8
-; CHECK-NEXT: v_mul_hi_u32 v13, v3, v8
-; CHECK-NEXT: v_mul_hi_u32 v8, v6, v8
-; CHECK-NEXT: v_add_i32_e32 v9, vcc, v10, v9
+; CHECK-NEXT: v_sub_i32_e32 v6, vcc, v6, v3
+; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
+; CHECK-NEXT: v_mul_lo_u32 v8, v5, v7
+; CHECK-NEXT: v_mul_hi_u32 v9, v3, v7
+; CHECK-NEXT: v_mul_hi_u32 v7, v5, v7
+; CHECK-NEXT: v_mul_lo_u32 v10, v3, v6
+; CHECK-NEXT: v_mul_lo_u32 v11, v5, v6
+; CHECK-NEXT: v_mul_hi_u32 v12, v3, v6
+; CHECK-NEXT: v_mul_hi_u32 v6, v5, v6
+; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v7, vcc, v12, v7
-; CHECK-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v9, vcc, v9, v11
-; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v13
+; CHECK-NEXT: v_add_i32_e32 v7, vcc, v11, v7
; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v9, vcc, v10, v9
-; CHECK-NEXT: v_add_i32_e32 v10, vcc, v12, v11
-; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v9
-; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v9
+; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v12
+; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; CHECK-NEXT: v_add_i32_e32 v8, vcc, v10, v8
+; CHECK-NEXT: v_add_i32_e32 v9, vcc, v11, v9
+; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8
+; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v7
-; CHECK-NEXT: v_addc_u32_e32 v6, vcc, v6, v8, vcc
-; CHECK-NEXT: v_mul_lo_u32 v7, v1, v3
-; CHECK-NEXT: v_mul_hi_u32 v8, v0, v3
-; CHECK-NEXT: v_mul_hi_u32 v3, v1, v3
-; CHECK-NEXT: v_mul_lo_u32 v9, v0, v6
-; CHECK-NEXT: v_mul_lo_u32 v10, v1, v6
-; CHECK-NEXT: v_mul_hi_u32 v11, v0, v6
-; CHECK-NEXT: v_mul_hi_u32 v6, v1, v6
-; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v9
+; CHECK-NEXT: v_addc_u32_e32 v5, vcc, v5, v6, vcc
+; CHECK-NEXT: v_mul_lo_u32 v6, v3, s5
+; CHECK-NEXT: v_mul_hi_u32 v7, s5, v3
+; CHECK-NEXT: v_mul_lo_u32 v8, v5, s5
+; CHECK-NEXT: v_mul_lo_u32 v9, v5, v6
+; CHECK-NEXT: v_mul_hi_u32 v10, v3, v6
+; CHECK-NEXT: v_mul_hi_u32 v6, v5, v6
+; CHECK-NEXT: v_sub_i32_e32 v8, vcc, v8, v3
+; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; CHECK-NEXT: v_mul_lo_u32 v8, v3, v7
+; CHECK-NEXT: v_mul_lo_u32 v11, v5, v7
+; CHECK-NEXT: v_mul_hi_u32 v12, v3, v7
+; CHECK-NEXT: v_mul_hi_u32 v7, v5, v7
+; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, v10, v3
+; CHECK-NEXT: v_add_i32_e32 v6, vcc, v11, v6
+; CHECK-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; CHECK-NEXT: v_add_i32_e32 v8, vcc, v8, v10
+; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v12
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
+; CHECK-NEXT: v_add_i32_e32 v9, vcc, v11, v10
+; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
+; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v7, v8
-; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v11
+; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v6
+; CHECK-NEXT: v_addc_u32_e32 v5, vcc, v5, v7, vcc
+; CHECK-NEXT: v_mul_lo_u32 v6, v1, v3
+; CHECK-NEXT: v_mul_hi_u32 v7, v0, v3
+; CHECK-NEXT: v_mul_hi_u32 v3, v1, v3
+; CHECK-NEXT: v_mul_lo_u32 v8, v0, v5
+; CHECK-NEXT: v_mul_lo_u32 v9, v1, v5
+; CHECK-NEXT: v_mul_hi_u32 v10, v0, v5
+; CHECK-NEXT: v_mul_hi_u32 v5, v1, v5
+; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v7
-; CHECK-NEXT: v_add_i32_e32 v8, vcc, v10, v8
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v7
+; CHECK-NEXT: v_add_i32_e32 v3, vcc, v9, v3
+; CHECK-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v7
+; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v10
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
-; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
-; CHECK-NEXT: v_mul_lo_u32 v8, v3, s4
+; CHECK-NEXT: v_add_i32_e32 v6, vcc, v8, v6
+; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v7
+; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v6
+; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
+; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
+; CHECK-NEXT: v_mul_lo_u32 v7, v3, s4
; CHECK-NEXT: v_mul_hi_u32 v3, s4, v3
-; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v7
-; CHECK-NEXT: v_mul_lo_u32 v6, v6, s4
-; CHECK-NEXT: v_add_i32_e32 v3, vcc, v6, v3
-; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v8
-; CHECK-NEXT: v_subb_u32_e64 v6, s[4:5], v1, v3, vcc
+; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
+; CHECK-NEXT: v_mul_lo_u32 v5, v5, s4
+; CHECK-NEXT: v_add_i32_e32 v3, vcc, v5, v3
+; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v7
+; CHECK-NEXT: v_subb_u32_e64 v5, s[4:5], v1, v3, vcc
; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v3
; CHECK-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v2
; CHECK-NEXT: v_cndmask_b32_e64 v3, 0, -1, s[4:5]
-; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v6
+; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v5
; CHECK-NEXT: v_cndmask_b32_e64 v3, v4, v3, s[4:5]
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT: v_sub_i32_e32 v4, vcc, v0, v2
+; CHECK-NEXT: v_sub_i32_e32 v6, vcc, v0, v2
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v4, v2
+; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v6, v2
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, -1, vcc
-; CHECK-NEXT: v_sub_i32_e32 v2, vcc, v4, v2
+; CHECK-NEXT: v_sub_i32_e32 v2, vcc, v6, v2
; CHECK-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1
-; CHECK-NEXT: v_cndmask_b32_e64 v5, v5, v7, s[4:5]
+; CHECK-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[4:5]
; CHECK-NEXT: v_subbrev_u32_e32 v7, vcc, 0, v1, vcc
-; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
-; CHECK-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
+; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
+; CHECK-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
-; CHECK-NEXT: v_cndmask_b32_e32 v1, v6, v1, vcc
+; CHECK-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; CHECK-NEXT: s_setpc_b64 s[30:31]
%result = urem i64 %num, 1235195
ret i64 %result
; GISEL-LABEL: v_urem_v2i64_oddk_denom:
; GISEL: ; %bb.0:
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GISEL-NEXT: s_mov_b32 s8, 0x12d8fb
+; GISEL-NEXT: s_mov_b32 s6, 0x12d8fb
; GISEL-NEXT: v_mov_b32_e32 v4, 0x12d8fb
-; GISEL-NEXT: v_cvt_f32_u32_e32 v7, 0x12d8fb
+; GISEL-NEXT: v_cvt_f32_u32_e32 v6, 0x12d8fb
; GISEL-NEXT: v_cvt_f32_ubyte0_e32 v5, 0
-; GISEL-NEXT: s_sub_u32 s6, 0, 0x12d8fb
-; GISEL-NEXT: v_madmk_f32 v6, v5, 0x4f800000, v7
-; GISEL-NEXT: s_subb_u32 s7, 0, 0
-; GISEL-NEXT: s_bfe_i32 s4, -1, 0x10000
-; GISEL-NEXT: s_bfe_i32 s5, -1, 0x10000
-; GISEL-NEXT: v_mac_f32_e32 v7, 0x4f800000, v5
-; GISEL-NEXT: v_rcp_iflag_f32_e32 v8, v6
-; GISEL-NEXT: v_mov_b32_e32 v6, s4
-; GISEL-NEXT: v_mov_b32_e32 v5, s5
+; GISEL-NEXT: s_sub_u32 s7, 0, 0x12d8fb
+; GISEL-NEXT: v_madmk_f32 v7, v5, 0x4f800000, v6
+; GISEL-NEXT: s_subb_u32 s8, 0, 0
+; GISEL-NEXT: s_bfe_i32 s4, 1, 0x10000
+; GISEL-NEXT: v_mac_f32_e32 v6, 0x4f800000, v5
; GISEL-NEXT: v_rcp_iflag_f32_e32 v7, v7
+; GISEL-NEXT: v_mov_b32_e32 v5, s4
+; GISEL-NEXT: v_rcp_iflag_f32_e32 v6, v6
; GISEL-NEXT: s_sub_u32 s9, 0, 0x12d8fb
-; GISEL-NEXT: v_mul_f32_e32 v8, 0x5f7ffffc, v8
; GISEL-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v7
+; GISEL-NEXT: v_mul_f32_e32 v6, 0x5f7ffffc, v6
; GISEL-NEXT: s_subb_u32 s10, 0, 0
-; GISEL-NEXT: s_bfe_i32 s11, -1, 0x10000
-; GISEL-NEXT: s_bfe_i32 s12, -1, 0x10000
-; GISEL-NEXT: v_mul_f32_e32 v9, 0x2f800000, v8
-; GISEL-NEXT: v_mul_f32_e32 v10, 0x2f800000, v7
+; GISEL-NEXT: s_bfe_i32 s4, 1, 0x10000
+; GISEL-NEXT: v_mul_f32_e32 v8, 0x2f800000, v7
+; GISEL-NEXT: v_mul_f32_e32 v9, 0x2f800000, v6
+; GISEL-NEXT: v_mov_b32_e32 v10, s4
+; GISEL-NEXT: v_trunc_f32_e32 v8, v8
; GISEL-NEXT: v_trunc_f32_e32 v9, v9
-; GISEL-NEXT: v_trunc_f32_e32 v10, v10
-; GISEL-NEXT: v_mac_f32_e32 v8, 0xcf800000, v9
-; GISEL-NEXT: v_cvt_u32_f32_e32 v9, v9
-; GISEL-NEXT: v_mac_f32_e32 v7, 0xcf800000, v10
-; GISEL-NEXT: v_cvt_u32_f32_e32 v10, v10
+; GISEL-NEXT: v_mac_f32_e32 v7, 0xcf800000, v8
; GISEL-NEXT: v_cvt_u32_f32_e32 v8, v8
-; GISEL-NEXT: v_mul_lo_u32 v11, s6, v9
+; GISEL-NEXT: v_mac_f32_e32 v6, 0xcf800000, v9
+; GISEL-NEXT: v_cvt_u32_f32_e32 v9, v9
; GISEL-NEXT: v_cvt_u32_f32_e32 v7, v7
-; GISEL-NEXT: v_mul_lo_u32 v12, s9, v10
-; GISEL-NEXT: v_mul_lo_u32 v13, s6, v8
-; GISEL-NEXT: v_mul_lo_u32 v14, s7, v8
-; GISEL-NEXT: v_mul_hi_u32 v15, s6, v8
-; GISEL-NEXT: v_mul_lo_u32 v16, s9, v7
-; GISEL-NEXT: v_mul_lo_u32 v17, s10, v7
-; GISEL-NEXT: v_mul_hi_u32 v18, s9, v7
+; GISEL-NEXT: v_mul_lo_u32 v11, s7, v8
+; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GISEL-NEXT: v_mul_lo_u32 v12, s9, v9
+; GISEL-NEXT: v_mul_lo_u32 v13, s7, v7
+; GISEL-NEXT: v_mul_lo_u32 v14, s8, v7
+; GISEL-NEXT: v_mul_hi_u32 v15, s7, v7
+; GISEL-NEXT: v_mul_lo_u32 v16, s9, v6
+; GISEL-NEXT: v_mul_lo_u32 v17, s10, v6
+; GISEL-NEXT: v_mul_hi_u32 v18, s9, v6
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v14, v11
-; GISEL-NEXT: v_mul_lo_u32 v14, v9, v13
-; GISEL-NEXT: v_mul_hi_u32 v19, v8, v13
-; GISEL-NEXT: v_mul_hi_u32 v13, v9, v13
+; GISEL-NEXT: v_mul_lo_u32 v14, v8, v13
+; GISEL-NEXT: v_mul_hi_u32 v19, v7, v13
+; GISEL-NEXT: v_mul_hi_u32 v13, v8, v13
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v17, v12
-; GISEL-NEXT: v_mul_lo_u32 v17, v10, v16
+; GISEL-NEXT: v_mul_lo_u32 v17, v9, v16
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v15
-; GISEL-NEXT: v_mul_hi_u32 v15, v7, v16
-; GISEL-NEXT: v_mul_hi_u32 v16, v10, v16
+; GISEL-NEXT: v_mul_hi_u32 v15, v6, v16
+; GISEL-NEXT: v_mul_hi_u32 v16, v9, v16
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v18
-; GISEL-NEXT: v_mul_lo_u32 v18, v7, v12
+; GISEL-NEXT: v_mul_lo_u32 v18, v6, v12
; GISEL-NEXT: v_add_i32_e32 v17, vcc, v17, v18
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v17, v15
-; GISEL-NEXT: v_mul_lo_u32 v15, v8, v11
-; GISEL-NEXT: v_mul_lo_u32 v17, v9, v11
+; GISEL-NEXT: v_mul_lo_u32 v15, v7, v11
+; GISEL-NEXT: v_mul_lo_u32 v17, v8, v11
; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v14, v15
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v14, v19
-; GISEL-NEXT: v_mul_hi_u32 v14, v8, v11
-; GISEL-NEXT: v_mul_hi_u32 v11, v9, v11
+; GISEL-NEXT: v_mul_hi_u32 v14, v7, v11
+; GISEL-NEXT: v_mul_hi_u32 v11, v8, v11
; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v15, s[4:5], v15, v19
-; GISEL-NEXT: v_mul_lo_u32 v19, v10, v12
+; GISEL-NEXT: v_mul_lo_u32 v19, v9, v12
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v17, v13
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v13, s[4:5], v13, v14
; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v17, v14
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v17, vcc, v18, v17
-; GISEL-NEXT: v_mul_hi_u32 v18, v7, v12
-; GISEL-NEXT: v_mul_hi_u32 v12, v10, v12
+; GISEL-NEXT: v_mul_hi_u32 v18, v6, v12
+; GISEL-NEXT: v_mul_hi_u32 v12, v9, v12
; GISEL-NEXT: v_add_i32_e32 v16, vcc, v19, v16
; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v16, vcc, v16, v18
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v18, v17
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v14
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v15
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v13
-; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v9, v11, vcc
-; GISEL-NEXT: v_mul_lo_u32 v11, s6, v8
-; GISEL-NEXT: v_mul_lo_u32 v13, s7, v8
-; GISEL-NEXT: v_mul_hi_u32 v14, s6, v8
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v16
-; GISEL-NEXT: v_addc_u32_e32 v10, vcc, v10, v12, vcc
-; GISEL-NEXT: v_mul_lo_u32 v12, s9, v7
-; GISEL-NEXT: v_mul_lo_u32 v15, s10, v7
-; GISEL-NEXT: v_mul_hi_u32 v16, s9, v7
-; GISEL-NEXT: v_mul_lo_u32 v17, s6, v9
-; GISEL-NEXT: v_mul_lo_u32 v18, v9, v11
-; GISEL-NEXT: v_mul_hi_u32 v19, v8, v11
-; GISEL-NEXT: v_mul_hi_u32 v11, v9, v11
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v13
+; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v8, v11, vcc
+; GISEL-NEXT: v_mul_lo_u32 v11, s7, v7
+; GISEL-NEXT: v_mul_lo_u32 v13, s8, v7
+; GISEL-NEXT: v_mul_hi_u32 v14, s7, v7
+; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v16
+; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v9, v12, vcc
+; GISEL-NEXT: v_mul_lo_u32 v12, s9, v6
+; GISEL-NEXT: v_mul_lo_u32 v15, s10, v6
+; GISEL-NEXT: v_mul_hi_u32 v16, s9, v6
+; GISEL-NEXT: v_mul_lo_u32 v17, s7, v8
+; GISEL-NEXT: v_mul_lo_u32 v18, v8, v11
+; GISEL-NEXT: v_mul_hi_u32 v19, v7, v11
+; GISEL-NEXT: v_mul_hi_u32 v11, v8, v11
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v17
-; GISEL-NEXT: v_mul_lo_u32 v17, s9, v10
+; GISEL-NEXT: v_mul_lo_u32 v17, s9, v9
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v17
-; GISEL-NEXT: v_mul_lo_u32 v17, v10, v12
+; GISEL-NEXT: v_mul_lo_u32 v17, v9, v12
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
-; GISEL-NEXT: v_mul_hi_u32 v14, v7, v12
-; GISEL-NEXT: v_mul_hi_u32 v12, v10, v12
+; GISEL-NEXT: v_mul_hi_u32 v14, v6, v12
+; GISEL-NEXT: v_mul_hi_u32 v12, v9, v12
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v16
-; GISEL-NEXT: v_mul_lo_u32 v16, v7, v15
+; GISEL-NEXT: v_mul_lo_u32 v16, v6, v15
; GISEL-NEXT: v_add_i32_e32 v16, vcc, v17, v16
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v16, v14
-; GISEL-NEXT: v_mul_lo_u32 v14, v8, v13
-; GISEL-NEXT: v_mul_lo_u32 v16, v9, v13
+; GISEL-NEXT: v_mul_lo_u32 v14, v7, v13
+; GISEL-NEXT: v_mul_lo_u32 v16, v8, v13
; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v18, v14
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v14, v19
-; GISEL-NEXT: v_mul_hi_u32 v14, v8, v13
+; GISEL-NEXT: v_mul_hi_u32 v14, v7, v13
+; GISEL-NEXT: v_mul_hi_u32 v13, v8, v13
; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v18, s[4:5], v18, v19
-; GISEL-NEXT: v_mul_lo_u32 v19, v10, v15
+; GISEL-NEXT: v_mul_lo_u32 v19, v9, v15
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v16, v11
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14
; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v16, v14
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v16, vcc, v17, v16
-; GISEL-NEXT: v_mul_hi_u32 v17, v7, v15
+; GISEL-NEXT: v_mul_hi_u32 v17, v6, v15
+; GISEL-NEXT: v_mul_hi_u32 v15, v9, v15
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v19, v12
; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v17
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v17, vcc, v19, v17
-; GISEL-NEXT: v_mov_b32_e32 v19, s11
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v18
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v18
-; GISEL-NEXT: v_mov_b32_e32 v18, s12
-; GISEL-NEXT: v_mul_hi_u32 v13, v9, v13
-; GISEL-NEXT: v_mul_hi_u32 v15, v10, v15
; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v16
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v18
; GISEL-NEXT: v_add_i32_e32 v16, vcc, v17, v16
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v16
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v11
-; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v9, v13, vcc
-; GISEL-NEXT: v_mul_lo_u32 v11, v1, v8
-; GISEL-NEXT: v_mul_hi_u32 v13, v0, v8
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v11
+; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v8, v13, vcc
+; GISEL-NEXT: v_mul_lo_u32 v11, v1, v7
+; GISEL-NEXT: v_mul_hi_u32 v13, v0, v7
+; GISEL-NEXT: v_mul_hi_u32 v7, v1, v7
+; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v12
+; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v9, v14, vcc
+; GISEL-NEXT: v_mul_lo_u32 v12, v3, v6
+; GISEL-NEXT: v_mul_hi_u32 v14, v2, v6
+; GISEL-NEXT: v_mul_hi_u32 v6, v3, v6
+; GISEL-NEXT: v_mul_lo_u32 v15, v0, v8
+; GISEL-NEXT: v_mul_lo_u32 v16, v1, v8
+; GISEL-NEXT: v_mul_hi_u32 v17, v0, v8
; GISEL-NEXT: v_mul_hi_u32 v8, v1, v8
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v12
-; GISEL-NEXT: v_addc_u32_e32 v10, vcc, v10, v14, vcc
-; GISEL-NEXT: v_mul_lo_u32 v12, v3, v7
-; GISEL-NEXT: v_mul_hi_u32 v14, v2, v7
-; GISEL-NEXT: v_mul_hi_u32 v7, v3, v7
-; GISEL-NEXT: v_mul_lo_u32 v15, v0, v9
-; GISEL-NEXT: v_mul_lo_u32 v16, v1, v9
-; GISEL-NEXT: v_mul_hi_u32 v17, v0, v9
-; GISEL-NEXT: v_mul_hi_u32 v9, v1, v9
+; GISEL-NEXT: v_mul_lo_u32 v18, v2, v9
+; GISEL-NEXT: v_mul_lo_u32 v19, v3, v9
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v15
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v13
-; GISEL-NEXT: v_mul_lo_u32 v11, v2, v10
-; GISEL-NEXT: v_mul_lo_u32 v13, v3, v10
-; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v12, v11
-; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14
-; GISEL-NEXT: v_mul_hi_u32 v11, v2, v10
-; GISEL-NEXT: v_mul_hi_u32 v10, v3, v10
-; GISEL-NEXT: v_add_i32_e64 v8, s[6:7], v16, v8
-; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[6:7]
-; GISEL-NEXT: v_add_i32_e64 v7, s[6:7], v13, v7
-; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[6:7]
-; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v17
-; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v16
+; GISEL-NEXT: v_mul_hi_u32 v11, v2, v9
+; GISEL-NEXT: v_mul_hi_u32 v9, v3, v9
+; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v16, v7
+; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
+; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v18
; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v11
+; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v19, v6
+; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v17
+; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v14
+; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v11
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v17
-; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v16
-; GISEL-NEXT: v_add_i32_e32 v11, vcc, v13, v11
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v15
-; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v12
+; GISEL-NEXT: v_add_i32_e32 v14, vcc, v15, v19
+; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v17
+; GISEL-NEXT: v_add_i32_e32 v12, vcc, v16, v12
+; GISEL-NEXT: v_add_i32_e32 v11, vcc, v18, v11
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v14
+; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v12
; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13
-; GISEL-NEXT: v_mul_lo_u32 v14, v8, s8
-; GISEL-NEXT: v_mul_hi_u32 v8, s8, v8
+; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
+; GISEL-NEXT: v_mul_lo_u32 v14, v7, s6
+; GISEL-NEXT: v_mul_hi_u32 v7, s6, v7
; GISEL-NEXT: v_add_i32_e32 v11, vcc, v11, v12
-; GISEL-NEXT: v_mul_lo_u32 v12, v7, s8
-; GISEL-NEXT: v_mul_hi_u32 v7, s8, v7
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v13
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
-; GISEL-NEXT: v_mul_lo_u32 v9, v9, s8
-; GISEL-NEXT: v_mul_lo_u32 v10, v10, s8
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v9, v8
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, v10, v7
+; GISEL-NEXT: v_mul_lo_u32 v12, v6, s6
+; GISEL-NEXT: v_mul_hi_u32 v6, s6, v6
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v13
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT: v_mul_lo_u32 v8, v8, s6
+; GISEL-NEXT: v_mul_lo_u32 v9, v9, s6
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v7
+; GISEL-NEXT: v_add_i32_e32 v6, vcc, v9, v6
; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v14
-; GISEL-NEXT: v_subb_u32_e64 v9, s[4:5], v1, v8, vcc
-; GISEL-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v8
+; GISEL-NEXT: v_subb_u32_e64 v8, s[4:5], v1, v7, vcc
+; GISEL-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v7
; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], v2, v12
-; GISEL-NEXT: v_subb_u32_e64 v10, s[6:7], v3, v7, s[4:5]
-; GISEL-NEXT: v_sub_i32_e64 v3, s[6:7], v3, v7
+; GISEL-NEXT: v_subb_u32_e64 v9, s[6:7], v3, v6, s[4:5]
+; GISEL-NEXT: v_sub_i32_e64 v3, s[6:7], v3, v6
; GISEL-NEXT: v_cmp_ge_u32_e64 s[6:7], v2, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[6:7]
-; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v9
-; GISEL-NEXT: v_cndmask_b32_e64 v6, v6, v8, s[6:7]
+; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[6:7]
+; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v8
+; GISEL-NEXT: v_cndmask_b32_e64 v7, v5, v7, s[6:7]
; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v10
-; GISEL-NEXT: v_cndmask_b32_e32 v7, v19, v7, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
+; GISEL-NEXT: v_cndmask_b32_e32 v6, v5, v6, vcc
; GISEL-NEXT: v_subbrev_u32_e64 v3, vcc, 0, v3, s[4:5]
-; GISEL-NEXT: v_sub_i32_e32 v8, vcc, v0, v4
+; GISEL-NEXT: v_sub_i32_e32 v11, vcc, v0, v4
; GISEL-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v8, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc
-; GISEL-NEXT: v_sub_i32_e32 v12, vcc, v2, v4
+; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v11, v4
+; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc
+; GISEL-NEXT: v_sub_i32_e32 v13, vcc, v2, v4
; GISEL-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
-; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v12, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc
+; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v13, v4
+; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, -1, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; GISEL-NEXT: v_cndmask_b32_e32 v5, v5, v11, vcc
-; GISEL-NEXT: v_sub_i32_e32 v11, vcc, v8, v4
-; GISEL-NEXT: v_subbrev_u32_e32 v14, vcc, 0, v1, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v5, v5, v12, vcc
+; GISEL-NEXT: v_sub_i32_e32 v12, vcc, v11, v4
+; GISEL-NEXT: v_subbrev_u32_e32 v15, vcc, 0, v1, vcc
; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
-; GISEL-NEXT: v_cndmask_b32_e32 v13, v18, v13, vcc
-; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v12, v4
-; GISEL-NEXT: v_subbrev_u32_e32 v15, vcc, 0, v3, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v10, v10, v14, vcc
+; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v13, v4
+; GISEL-NEXT: v_subbrev_u32_e32 v14, vcc, 0, v3, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
-; GISEL-NEXT: v_cndmask_b32_e32 v5, v8, v11, vcc
-; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v13
-; GISEL-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v14, vcc
-; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
+; GISEL-NEXT: v_cndmask_b32_e32 v5, v11, v12, vcc
+; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v10
+; GISEL-NEXT: v_cndmask_b32_e64 v4, v13, v4, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc
+; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v3, v3, v15, s[4:5]
-; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v7
+; GISEL-NEXT: v_cndmask_b32_e64 v3, v3, v14, s[4:5]
+; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v6
; GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v3, v10, v3, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v3, v9, v3, s[4:5]
; GISEL-NEXT: s_setpc_b64 s[30:31]
;
; CGP-LABEL: v_urem_v2i64_oddk_denom:
; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; CGP-NEXT: s_mov_b32 s8, 0x12d8fb
+; CGP-NEXT: s_mov_b32 s6, 0x12d8fb
; CGP-NEXT: v_mov_b32_e32 v4, 0x12d8fb
-; CGP-NEXT: v_cvt_f32_u32_e32 v5, 0x12d8fb
-; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0
-; CGP-NEXT: s_mov_b32 s6, 0xffed2705
-; CGP-NEXT: s_bfe_i32 s4, -1, 0x10000
-; CGP-NEXT: s_bfe_i32 s5, -1, 0x10000
+; CGP-NEXT: v_cvt_f32_u32_e32 v6, 0x12d8fb
+; CGP-NEXT: v_cvt_f32_ubyte0_e32 v5, 0
+; CGP-NEXT: s_mov_b32 s7, 0xffed2705
+; CGP-NEXT: s_bfe_i32 s4, 1, 0x10000
; CGP-NEXT: v_cvt_f32_u32_e32 v7, 0x12d8fb
; CGP-NEXT: v_cvt_f32_ubyte0_e32 v8, 0
-; CGP-NEXT: s_bfe_i32 s7, -1, 0x10000
-; CGP-NEXT: s_bfe_i32 s9, -1, 0x10000
-; CGP-NEXT: v_mac_f32_e32 v5, 0x4f800000, v6
-; CGP-NEXT: v_mov_b32_e32 v6, s4
-; CGP-NEXT: v_mov_b32_e32 v9, s5
+; CGP-NEXT: v_mac_f32_e32 v6, 0x4f800000, v5
+; CGP-NEXT: v_mov_b32_e32 v5, s4
; CGP-NEXT: v_mac_f32_e32 v7, 0x4f800000, v8
-; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v5
+; CGP-NEXT: v_rcp_iflag_f32_e32 v6, v6
; CGP-NEXT: v_rcp_iflag_f32_e32 v7, v7
-; CGP-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
+; CGP-NEXT: v_mul_f32_e32 v6, 0x5f7ffffc, v6
; CGP-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v7
-; CGP-NEXT: v_mul_f32_e32 v8, 0x2f800000, v5
-; CGP-NEXT: v_mul_f32_e32 v10, 0x2f800000, v7
+; CGP-NEXT: v_mul_f32_e32 v8, 0x2f800000, v6
+; CGP-NEXT: v_mul_f32_e32 v9, 0x2f800000, v7
; CGP-NEXT: v_trunc_f32_e32 v8, v8
-; CGP-NEXT: v_trunc_f32_e32 v10, v10
-; CGP-NEXT: v_mac_f32_e32 v5, 0xcf800000, v8
+; CGP-NEXT: v_trunc_f32_e32 v9, v9
+; CGP-NEXT: v_mac_f32_e32 v6, 0xcf800000, v8
; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8
-; CGP-NEXT: v_mac_f32_e32 v7, 0xcf800000, v10
-; CGP-NEXT: v_cvt_u32_f32_e32 v10, v10
-; CGP-NEXT: v_cvt_u32_f32_e32 v5, v5
-; CGP-NEXT: v_mul_lo_u32 v11, v8, s6
+; CGP-NEXT: v_mac_f32_e32 v7, 0xcf800000, v9
+; CGP-NEXT: v_cvt_u32_f32_e32 v9, v9
+; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6
+; CGP-NEXT: v_mul_lo_u32 v10, v8, s7
; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
-; CGP-NEXT: v_mul_lo_u32 v12, v10, s6
-; CGP-NEXT: v_mul_lo_u32 v13, v5, s6
-; CGP-NEXT: v_mul_hi_u32 v14, s6, v5
-; CGP-NEXT: v_sub_i32_e32 v11, vcc, v11, v5
-; CGP-NEXT: v_mul_lo_u32 v15, v7, s6
-; CGP-NEXT: v_mul_hi_u32 v16, s6, v7
-; CGP-NEXT: v_sub_i32_e32 v12, vcc, v12, v7
-; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v14
-; CGP-NEXT: v_mul_lo_u32 v14, v8, v13
-; CGP-NEXT: v_mul_hi_u32 v17, v5, v13
-; CGP-NEXT: v_mul_hi_u32 v13, v8, v13
-; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v16
-; CGP-NEXT: v_mul_lo_u32 v16, v10, v15
-; CGP-NEXT: v_mul_hi_u32 v18, v7, v15
-; CGP-NEXT: v_mul_hi_u32 v15, v10, v15
-; CGP-NEXT: v_mul_lo_u32 v19, v7, v12
-; CGP-NEXT: v_add_i32_e32 v16, vcc, v16, v19
+; CGP-NEXT: v_mul_lo_u32 v11, v9, s7
+; CGP-NEXT: v_mul_lo_u32 v12, v6, s7
+; CGP-NEXT: v_mul_hi_u32 v13, s7, v6
+; CGP-NEXT: v_sub_i32_e32 v10, vcc, v10, v6
+; CGP-NEXT: v_mul_lo_u32 v14, v7, s7
+; CGP-NEXT: v_mul_hi_u32 v15, s7, v7
+; CGP-NEXT: v_sub_i32_e32 v11, vcc, v11, v7
+; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13
+; CGP-NEXT: v_mul_lo_u32 v13, v8, v12
+; CGP-NEXT: v_mul_hi_u32 v16, v6, v12
+; CGP-NEXT: v_mul_hi_u32 v12, v8, v12
+; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v15
+; CGP-NEXT: v_mul_lo_u32 v15, v9, v14
+; CGP-NEXT: v_mul_hi_u32 v17, v7, v14
+; CGP-NEXT: v_mul_hi_u32 v14, v9, v14
+; CGP-NEXT: v_mul_lo_u32 v18, v6, v10
+; CGP-NEXT: v_mul_lo_u32 v19, v7, v11
+; CGP-NEXT: v_add_i32_e32 v15, vcc, v15, v19
; CGP-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v16, vcc, v16, v18
-; CGP-NEXT: v_mul_lo_u32 v16, v5, v11
-; CGP-NEXT: v_mul_lo_u32 v18, v8, v11
-; CGP-NEXT: v_add_i32_e64 v14, s[4:5], v14, v16
-; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; CGP-NEXT: v_add_i32_e64 v14, s[4:5], v14, v17
-; CGP-NEXT: v_mul_hi_u32 v14, v5, v11
-; CGP-NEXT: v_mul_hi_u32 v11, v8, v11
-; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[4:5]
-; CGP-NEXT: v_add_i32_e64 v16, s[4:5], v16, v17
-; CGP-NEXT: v_mul_lo_u32 v17, v10, v12
-; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v18, v13
+; CGP-NEXT: v_add_i32_e32 v15, vcc, v15, v17
+; CGP-NEXT: v_mul_lo_u32 v15, v8, v10
+; CGP-NEXT: v_mul_hi_u32 v17, v6, v10
+; CGP-NEXT: v_mul_hi_u32 v10, v8, v10
+; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v18
; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[4:5]
+; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v16
+; CGP-NEXT: v_mul_lo_u32 v13, v9, v11
+; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5]
+; CGP-NEXT: v_add_i32_e64 v16, s[4:5], v18, v16
+; CGP-NEXT: v_mul_hi_u32 v18, v7, v11
+; CGP-NEXT: v_mul_hi_u32 v11, v9, v11
+; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v15, v12
+; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; CGP-NEXT: v_add_i32_e64 v14, s[4:5], v18, v14
-; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v18, vcc, v19, v18
-; CGP-NEXT: v_mul_hi_u32 v19, v7, v12
-; CGP-NEXT: v_mul_hi_u32 v12, v10, v12
-; CGP-NEXT: v_add_i32_e32 v15, vcc, v17, v15
+; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v17
+; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[4:5]
+; CGP-NEXT: v_add_i32_e64 v15, s[4:5], v15, v17
; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v15, vcc, v15, v19
-; CGP-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v17, vcc, v17, v19
-; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v16
-; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v15, vcc, v15, v18
+; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v18
; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v16
-; CGP-NEXT: v_add_i32_e32 v16, vcc, v17, v18
-; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v14
+; CGP-NEXT: v_add_i32_e32 v17, vcc, v19, v17
+; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v18
; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v16
-; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v13
-; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v11, vcc
-; CGP-NEXT: v_mul_lo_u32 v11, v5, s6
-; CGP-NEXT: v_mul_hi_u32 v13, s6, v5
-; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v15
-; CGP-NEXT: v_addc_u32_e32 v10, vcc, v10, v12, vcc
-; CGP-NEXT: v_mul_lo_u32 v12, v7, s6
-; CGP-NEXT: v_mul_hi_u32 v14, s6, v7
-; CGP-NEXT: v_mul_lo_u32 v15, v8, s6
-; CGP-NEXT: v_mul_lo_u32 v16, v8, v11
-; CGP-NEXT: v_mul_hi_u32 v17, v5, v11
-; CGP-NEXT: v_mul_hi_u32 v11, v8, v11
-; CGP-NEXT: v_mul_lo_u32 v18, v10, s6
-; CGP-NEXT: v_mul_lo_u32 v19, v10, v12
-; CGP-NEXT: v_sub_i32_e32 v15, vcc, v15, v5
-; CGP-NEXT: v_add_i32_e32 v13, vcc, v15, v13
-; CGP-NEXT: v_mul_hi_u32 v15, v7, v12
-; CGP-NEXT: v_mul_hi_u32 v12, v10, v12
-; CGP-NEXT: v_sub_i32_e32 v18, vcc, v18, v7
-; CGP-NEXT: v_add_i32_e32 v14, vcc, v18, v14
-; CGP-NEXT: v_mul_lo_u32 v18, v7, v14
-; CGP-NEXT: v_add_i32_e32 v18, vcc, v19, v18
-; CGP-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v15, vcc, v18, v15
-; CGP-NEXT: v_mul_lo_u32 v15, v5, v13
-; CGP-NEXT: v_mul_lo_u32 v18, v8, v13
-; CGP-NEXT: v_add_i32_e64 v15, s[4:5], v16, v15
+; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v17
+; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v15, vcc, v15, v16
+; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v17
+; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v15
+; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v14
+; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v12
+; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v10, vcc
+; CGP-NEXT: v_mul_lo_u32 v10, v6, s7
+; CGP-NEXT: v_mul_hi_u32 v12, s7, v6
+; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v13
+; CGP-NEXT: v_addc_u32_e32 v9, vcc, v9, v11, vcc
+; CGP-NEXT: v_mul_lo_u32 v11, v7, s7
+; CGP-NEXT: v_mul_hi_u32 v13, s7, v7
+; CGP-NEXT: v_mul_lo_u32 v14, v8, s7
+; CGP-NEXT: v_mul_lo_u32 v15, v8, v10
+; CGP-NEXT: v_mul_hi_u32 v16, v6, v10
+; CGP-NEXT: v_mul_hi_u32 v10, v8, v10
+; CGP-NEXT: v_mul_lo_u32 v17, v9, s7
+; CGP-NEXT: v_mul_lo_u32 v18, v9, v11
+; CGP-NEXT: v_mul_hi_u32 v19, v7, v11
+; CGP-NEXT: v_mul_hi_u32 v11, v9, v11
+; CGP-NEXT: v_sub_i32_e32 v14, vcc, v14, v6
+; CGP-NEXT: v_sub_i32_e32 v17, vcc, v17, v7
+; CGP-NEXT: v_add_i32_e32 v12, vcc, v14, v12
+; CGP-NEXT: v_add_i32_e32 v13, vcc, v17, v13
+; CGP-NEXT: v_mul_lo_u32 v14, v6, v12
+; CGP-NEXT: v_mul_lo_u32 v17, v7, v13
+; CGP-NEXT: v_add_i32_e32 v17, vcc, v18, v17
+; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v17, vcc, v17, v19
+; CGP-NEXT: v_mul_lo_u32 v17, v8, v12
+; CGP-NEXT: v_mul_hi_u32 v19, v6, v12
+; CGP-NEXT: v_mul_hi_u32 v12, v8, v12
+; CGP-NEXT: v_add_i32_e64 v14, s[4:5], v15, v14
+; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5]
+; CGP-NEXT: v_add_i32_e64 v14, s[4:5], v14, v16
+; CGP-NEXT: v_mul_lo_u32 v14, v9, v13
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5]
-; CGP-NEXT: v_add_i32_e64 v15, s[4:5], v15, v17
-; CGP-NEXT: v_mul_hi_u32 v15, v5, v13
+; CGP-NEXT: v_add_i32_e64 v15, s[4:5], v15, v16
+; CGP-NEXT: v_mul_hi_u32 v16, v7, v13
+; CGP-NEXT: v_mul_hi_u32 v13, v9, v13
+; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v17, v10
; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[4:5]
-; CGP-NEXT: v_add_i32_e64 v16, s[4:5], v16, v17
-; CGP-NEXT: v_mul_lo_u32 v17, v10, v14
-; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v18, v11
-; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[4:5]
-; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v15
-; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; CGP-NEXT: v_add_i32_e64 v15, s[4:5], v18, v15
-; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v18, vcc, v19, v18
-; CGP-NEXT: v_mul_hi_u32 v19, v7, v14
-; CGP-NEXT: v_add_i32_e32 v12, vcc, v17, v12
-; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v19
+; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v14, v11
+; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
+; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v19
+; CGP-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[4:5]
+; CGP-NEXT: v_add_i32_e64 v17, s[4:5], v17, v19
; CGP-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v17, vcc, v17, v19
-; CGP-NEXT: v_mov_b32_e32 v19, s7
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v16
; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v15, vcc, v15, v16
-; CGP-NEXT: v_mov_b32_e32 v16, s9
-; CGP-NEXT: v_mul_hi_u32 v13, v8, v13
-; CGP-NEXT: v_mul_hi_u32 v14, v10, v14
-; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v18
-; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v17, vcc, v17, v18
-; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v15
-; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v17
-; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v11
-; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v13, vcc
-; CGP-NEXT: v_mul_lo_u32 v11, v1, v5
-; CGP-NEXT: v_mul_hi_u32 v13, v0, v5
-; CGP-NEXT: v_mul_hi_u32 v5, v1, v5
-; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v12
-; CGP-NEXT: v_addc_u32_e32 v10, vcc, v10, v14, vcc
-; CGP-NEXT: v_mul_lo_u32 v12, v3, v7
-; CGP-NEXT: v_mul_hi_u32 v14, v2, v7
+; CGP-NEXT: v_add_i32_e32 v18, vcc, v18, v19
+; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v16
+; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v15
+; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v18
+; CGP-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v15, vcc, v17, v15
+; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v16
+; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v15
+; CGP-NEXT: v_add_i32_e32 v13, vcc, v13, v14
+; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v10
+; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v12, vcc
+; CGP-NEXT: v_mul_lo_u32 v10, v1, v6
+; CGP-NEXT: v_mul_hi_u32 v12, v0, v6
+; CGP-NEXT: v_mul_hi_u32 v6, v1, v6
+; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v11
+; CGP-NEXT: v_addc_u32_e32 v9, vcc, v9, v13, vcc
+; CGP-NEXT: v_mul_lo_u32 v11, v3, v7
+; CGP-NEXT: v_mul_hi_u32 v13, v2, v7
; CGP-NEXT: v_mul_hi_u32 v7, v3, v7
-; CGP-NEXT: v_mul_lo_u32 v15, v0, v8
-; CGP-NEXT: v_mul_lo_u32 v17, v1, v8
-; CGP-NEXT: v_mul_hi_u32 v18, v0, v8
+; CGP-NEXT: v_mul_lo_u32 v14, v0, v8
+; CGP-NEXT: v_mul_lo_u32 v15, v1, v8
+; CGP-NEXT: v_mul_hi_u32 v16, v0, v8
; CGP-NEXT: v_mul_hi_u32 v8, v1, v8
-; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v15
+; CGP-NEXT: v_mul_lo_u32 v17, v2, v9
+; CGP-NEXT: v_mul_lo_u32 v18, v3, v9
+; CGP-NEXT: v_mul_hi_u32 v19, v2, v9
+; CGP-NEXT: v_mul_hi_u32 v9, v3, v9
+; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v14
+; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v6, vcc, v15, v6
; CGP-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v13
-; CGP-NEXT: v_mul_lo_u32 v11, v2, v10
-; CGP-NEXT: v_mul_lo_u32 v13, v3, v10
-; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v12, v11
-; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14
-; CGP-NEXT: v_mul_hi_u32 v11, v2, v10
-; CGP-NEXT: v_mul_hi_u32 v10, v3, v10
-; CGP-NEXT: v_add_i32_e64 v5, s[6:7], v17, v5
-; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[6:7]
-; CGP-NEXT: v_add_i32_e64 v7, s[6:7], v13, v7
-; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[6:7]
+; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v17
; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v18
+; CGP-NEXT: v_add_i32_e32 v7, vcc, v18, v7
; CGP-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v15, vcc, v15, v17
-; CGP-NEXT: v_cndmask_b32_e64 v17, 0, 1, s[4:5]
+; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
+; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v16
+; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v13
+; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v19
+; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
+; CGP-NEXT: v_add_i32_e32 v10, vcc, v14, v10
+; CGP-NEXT: v_add_i32_e32 v12, vcc, v15, v12
+; CGP-NEXT: v_add_i32_e32 v11, vcc, v17, v11
+; CGP-NEXT: v_add_i32_e32 v13, vcc, v18, v13
+; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v10
+; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v11
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v14, vcc, v14, v18
-; CGP-NEXT: v_add_i32_e32 v12, vcc, v12, v17
+; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10
+; CGP-NEXT: v_mul_lo_u32 v12, v6, s6
+; CGP-NEXT: v_mul_hi_u32 v6, s6, v6
; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v11
-; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v15
-; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v12
-; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
-; CGP-NEXT: v_add_i32_e32 v13, vcc, v14, v13
-; CGP-NEXT: v_mul_lo_u32 v14, v5, s8
-; CGP-NEXT: v_mul_hi_u32 v5, s8, v5
-; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12
-; CGP-NEXT: v_mul_lo_u32 v12, v7, s8
-; CGP-NEXT: v_mul_hi_u32 v7, s8, v7
-; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v13
-; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v11
-; CGP-NEXT: v_mul_lo_u32 v8, v8, s8
-; CGP-NEXT: v_mul_lo_u32 v10, v10, s8
-; CGP-NEXT: v_add_i32_e32 v5, vcc, v8, v5
-; CGP-NEXT: v_add_i32_e32 v7, vcc, v10, v7
-; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v14
-; CGP-NEXT: v_subb_u32_e64 v8, s[4:5], v1, v5, vcc
-; CGP-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v5
+; CGP-NEXT: v_mul_lo_u32 v13, v7, s6
+; CGP-NEXT: v_mul_hi_u32 v7, s6, v7
+; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10
+; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
+; CGP-NEXT: v_mul_lo_u32 v8, v8, s6
+; CGP-NEXT: v_mul_lo_u32 v9, v9, s6
+; CGP-NEXT: v_add_i32_e32 v6, vcc, v8, v6
+; CGP-NEXT: v_add_i32_e32 v7, vcc, v9, v7
+; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v12
+; CGP-NEXT: v_subb_u32_e64 v8, s[4:5], v1, v6, vcc
+; CGP-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v6
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v4
-; CGP-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[4:5]
-; CGP-NEXT: v_sub_i32_e64 v2, s[4:5], v2, v12
-; CGP-NEXT: v_subb_u32_e64 v10, s[6:7], v3, v7, s[4:5]
+; CGP-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5]
+; CGP-NEXT: v_sub_i32_e64 v2, s[4:5], v2, v13
+; CGP-NEXT: v_subb_u32_e64 v9, s[6:7], v3, v7, s[4:5]
; CGP-NEXT: v_sub_i32_e64 v3, s[6:7], v3, v7
; CGP-NEXT: v_cmp_ge_u32_e64 s[6:7], v2, v4
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[6:7]
; CGP-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v8
-; CGP-NEXT: v_cndmask_b32_e64 v5, v6, v5, s[6:7]
+; CGP-NEXT: v_cndmask_b32_e64 v6, v5, v6, s[6:7]
; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v10
-; CGP-NEXT: v_cndmask_b32_e32 v6, v19, v7, vcc
+; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
+; CGP-NEXT: v_cndmask_b32_e32 v7, v5, v7, vcc
; CGP-NEXT: v_subbrev_u32_e64 v3, vcc, 0, v3, s[4:5]
-; CGP-NEXT: v_sub_i32_e32 v7, vcc, v0, v4
+; CGP-NEXT: v_sub_i32_e32 v10, vcc, v0, v4
; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
-; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v7, v4
+; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v10, v4
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc
; CGP-NEXT: v_sub_i32_e32 v12, vcc, v2, v4
; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v12, v4
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; CGP-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
-; CGP-NEXT: v_sub_i32_e32 v11, vcc, v7, v4
-; CGP-NEXT: v_subbrev_u32_e32 v14, vcc, 0, v1, vcc
+; CGP-NEXT: v_cndmask_b32_e32 v11, v5, v11, vcc
+; CGP-NEXT: v_sub_i32_e32 v14, vcc, v10, v4
+; CGP-NEXT: v_subbrev_u32_e32 v15, vcc, 0, v1, vcc
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
-; CGP-NEXT: v_cndmask_b32_e32 v13, v16, v13, vcc
+; CGP-NEXT: v_cndmask_b32_e32 v5, v5, v13, vcc
; CGP-NEXT: v_sub_i32_e32 v4, vcc, v12, v4
-; CGP-NEXT: v_subbrev_u32_e32 v15, vcc, 0, v3, vcc
-; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
-; CGP-NEXT: v_cndmask_b32_e32 v7, v7, v11, vcc
-; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v13
+; CGP-NEXT: v_subbrev_u32_e32 v13, vcc, 0, v3, vcc
+; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
+; CGP-NEXT: v_cndmask_b32_e32 v10, v10, v14, vcc
+; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5
; CGP-NEXT: v_cndmask_b32_e64 v4, v12, v4, s[4:5]
-; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v14, vcc
-; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
-; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc
-; CGP-NEXT: v_cndmask_b32_e64 v3, v3, v15, s[4:5]
-; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v6
+; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v15, vcc
+; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6
+; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc
+; CGP-NEXT: v_cndmask_b32_e64 v3, v3, v13, s[4:5]
+; CGP-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v7
; CGP-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[4:5]
; CGP-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
-; CGP-NEXT: v_cndmask_b32_e64 v3, v10, v3, s[4:5]
+; CGP-NEXT: v_cndmask_b32_e64 v3, v9, v3, s[4:5]
; CGP-NEXT: s_setpc_b64 s[30:31]
%result = urem <2 x i64> %num, <i64 1235195, i64 1235195>
ret <2 x i64> %result
; GISEL-NEXT: v_cvt_u32_f32_e32 v8, v8
; GISEL-NEXT: v_mac_f32_e32 v7, 0xcf800000, v11
; GISEL-NEXT: v_cvt_u32_f32_e32 v11, v11
-; GISEL-NEXT: v_cvt_u32_f32_e32 v12, v6
-; GISEL-NEXT: v_mul_lo_u32 v6, v4, v8
+; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6
+; GISEL-NEXT: v_mul_lo_u32 v12, v4, v8
; GISEL-NEXT: v_cvt_u32_f32_e32 v7, v7
; GISEL-NEXT: v_mul_lo_u32 v13, v9, v11
-; GISEL-NEXT: v_mul_lo_u32 v14, v4, v12
-; GISEL-NEXT: v_mul_lo_u32 v15, v5, v12
-; GISEL-NEXT: v_mul_hi_u32 v16, v4, v12
+; GISEL-NEXT: v_mul_lo_u32 v14, v4, v6
+; GISEL-NEXT: v_mul_lo_u32 v15, v5, v6
+; GISEL-NEXT: v_mul_hi_u32 v16, v4, v6
; GISEL-NEXT: v_mul_lo_u32 v17, v9, v7
; GISEL-NEXT: v_mul_lo_u32 v18, v10, v7
; GISEL-NEXT: v_mul_hi_u32 v19, v9, v7
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v15, v6
+; GISEL-NEXT: v_add_i32_e32 v12, vcc, v15, v12
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v18, v13
; GISEL-NEXT: v_mul_lo_u32 v15, v11, v17
; GISEL-NEXT: v_mul_hi_u32 v18, v7, v17
; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc
; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v18
; GISEL-NEXT: v_mul_lo_u32 v15, v8, v14
-; GISEL-NEXT: v_mul_hi_u32 v18, v12, v14
+; GISEL-NEXT: v_mul_hi_u32 v18, v6, v14
; GISEL-NEXT: v_mul_hi_u32 v14, v8, v14
; GISEL-NEXT: v_mul_hi_u32 v17, v11, v17
-; GISEL-NEXT: v_add_i32_e64 v16, s[4:5], v6, v16
-; GISEL-NEXT: v_mul_lo_u32 v6, v12, v16
-; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v15, v6
+; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v12, v16
+; GISEL-NEXT: v_mul_lo_u32 v16, v6, v12
+; GISEL-NEXT: v_add_i32_e64 v15, s[4:5], v15, v16
+; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, s[4:5]
+; GISEL-NEXT: v_add_i32_e64 v15, s[4:5], v15, v18
+; GISEL-NEXT: v_mul_lo_u32 v15, v8, v12
+; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[4:5]
+; GISEL-NEXT: v_add_i32_e64 v16, s[4:5], v16, v18
+; GISEL-NEXT: v_mul_hi_u32 v18, v6, v12
+; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v15, v14
; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v18
-; GISEL-NEXT: v_mul_lo_u32 v6, v8, v16
+; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v14, v18
; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[4:5]
; GISEL-NEXT: v_add_i32_e64 v15, s[4:5], v15, v18
-; GISEL-NEXT: v_mul_hi_u32 v18, v12, v16
-; GISEL-NEXT: v_add_i32_e64 v6, s[4:5], v6, v14
-; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v18, s[4:5], v6, v18
-; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v14, s[4:5], v14, v6
-; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v19, vcc, v19, v6
-; GISEL-NEXT: v_mul_lo_u32 v6, v11, v13
-; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v17
-; GISEL-NEXT: v_mul_hi_u32 v17, v7, v13
+; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v18, vcc, v19, v18
+; GISEL-NEXT: v_mul_lo_u32 v19, v11, v13
+; GISEL-NEXT: v_add_i32_e32 v17, vcc, v19, v17
+; GISEL-NEXT: v_mul_hi_u32 v19, v7, v13
; GISEL-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v17, vcc, v6, v17
-; GISEL-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v20, vcc, v20, v6
-; GISEL-NEXT: v_and_b32_e32 v6, 0xffffff, v0
-; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v2
-; GISEL-NEXT: s_bfe_i32 s4, -1, 0x10000
-; GISEL-NEXT: s_bfe_i32 s5, -1, 0x10000
-; GISEL-NEXT: s_bfe_i32 s6, -1, 0x10000
-; GISEL-NEXT: s_bfe_i32 s7, -1, 0x10000
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v18, v15
-; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v15
-; GISEL-NEXT: v_mov_b32_e32 v15, s4
; GISEL-NEXT: v_add_i32_e32 v17, vcc, v17, v19
-; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v18, vcc, v20, v18
-; GISEL-NEXT: v_mov_b32_e32 v19, s5
-; GISEL-NEXT: v_mul_hi_u32 v16, v8, v16
-; GISEL-NEXT: v_add_i32_e32 v14, vcc, v16, v14
-; GISEL-NEXT: v_mov_b32_e32 v16, s6
+; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v19, vcc, v20, v19
+; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v0
+; GISEL-NEXT: v_and_b32_e32 v2, 0xffffff, v2
+; GISEL-NEXT: s_bfe_i32 s4, 1, 0x10000
+; GISEL-NEXT: v_add_i32_e32 v14, vcc, v14, v16
+; GISEL-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v15, vcc, v15, v16
+; GISEL-NEXT: v_mov_b32_e32 v16, s4
+; GISEL-NEXT: v_mul_hi_u32 v12, v8, v12
; GISEL-NEXT: v_mul_hi_u32 v13, v11, v13
+; GISEL-NEXT: v_add_i32_e32 v17, vcc, v17, v18
+; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v18, vcc, v19, v18
+; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v15
; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v18
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v12, v2
-; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v8, v14, vcc
-; GISEL-NEXT: v_mul_lo_u32 v12, v4, v2
-; GISEL-NEXT: v_mul_lo_u32 v5, v5, v2
-; GISEL-NEXT: v_mul_hi_u32 v14, v4, v2
+; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v14
+; GISEL-NEXT: v_addc_u32_e32 v8, vcc, v8, v12, vcc
+; GISEL-NEXT: v_mul_lo_u32 v12, v4, v6
+; GISEL-NEXT: v_mul_lo_u32 v5, v5, v6
+; GISEL-NEXT: v_mul_hi_u32 v14, v4, v6
; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v17
; GISEL-NEXT: v_addc_u32_e32 v11, vcc, v11, v13, vcc
; GISEL-NEXT: v_mul_lo_u32 v13, v9, v7
; GISEL-NEXT: v_mul_lo_u32 v10, v10, v7
-; GISEL-NEXT: v_mul_hi_u32 v17, v9, v7
+; GISEL-NEXT: v_mul_hi_u32 v15, v9, v7
; GISEL-NEXT: v_mul_lo_u32 v4, v4, v8
-; GISEL-NEXT: v_mul_lo_u32 v18, v8, v12
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v5, v4
-; GISEL-NEXT: v_mul_hi_u32 v5, v2, v12
+; GISEL-NEXT: v_mul_lo_u32 v17, v8, v12
+; GISEL-NEXT: v_mul_hi_u32 v18, v6, v12
; GISEL-NEXT: v_mul_hi_u32 v12, v8, v12
; GISEL-NEXT: v_mul_lo_u32 v9, v9, v11
+; GISEL-NEXT: v_mul_lo_u32 v19, v11, v13
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v5, v4
+; GISEL-NEXT: v_mul_hi_u32 v5, v7, v13
+; GISEL-NEXT: v_mul_hi_u32 v13, v11, v13
; GISEL-NEXT: v_add_i32_e32 v9, vcc, v10, v9
-; GISEL-NEXT: v_mul_lo_u32 v10, v11, v13
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v14
-; GISEL-NEXT: v_mul_hi_u32 v14, v7, v13
-; GISEL-NEXT: v_mul_hi_u32 v13, v11, v13
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v17
-; GISEL-NEXT: v_mul_lo_u32 v17, v7, v9
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v17
-; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v14
-; GISEL-NEXT: v_mul_lo_u32 v10, v2, v4
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v15
+; GISEL-NEXT: v_mul_lo_u32 v10, v6, v4
; GISEL-NEXT: v_mul_lo_u32 v14, v8, v4
-; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v18, v10
-; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v10, v5
-; GISEL-NEXT: v_mul_hi_u32 v5, v2, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v18, v10
-; GISEL-NEXT: v_mul_lo_u32 v18, v11, v9
-; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v14, v12
-; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v12, v5
-; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v12, s[4:5], v14, v12
-; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v14, vcc, v17, v14
-; GISEL-NEXT: v_mul_hi_u32 v17, v7, v9
-; GISEL-NEXT: v_add_i32_e32 v13, vcc, v18, v13
-; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v17
-; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v17, vcc, v18, v17
-; GISEL-NEXT: v_mov_b32_e32 v18, s7
+; GISEL-NEXT: v_mul_hi_u32 v15, v6, v4
; GISEL-NEXT: v_mul_hi_u32 v4, v8, v4
+; GISEL-NEXT: v_add_i32_e32 v10, vcc, v17, v10
+; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v18
+; GISEL-NEXT: v_mul_lo_u32 v10, v7, v9
+; GISEL-NEXT: v_mul_lo_u32 v18, v11, v9
+; GISEL-NEXT: v_add_i32_e64 v10, s[4:5], v19, v10
+; GISEL-NEXT: v_cndmask_b32_e64 v19, 0, 1, s[4:5]
+; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v10, v5
+; GISEL-NEXT: v_mul_hi_u32 v5, v7, v9
; GISEL-NEXT: v_mul_hi_u32 v9, v11, v9
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v10
-; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v14
+; GISEL-NEXT: v_add_i32_e64 v10, s[6:7], v14, v12
+; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[6:7]
+; GISEL-NEXT: v_add_i32_e64 v13, s[6:7], v18, v13
+; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[6:7]
+; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v15
+; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v17, vcc, v17, v18
+; GISEL-NEXT: v_cndmask_b32_e64 v18, 0, 1, s[4:5]
+; GISEL-NEXT: v_add_i32_e32 v5, vcc, v13, v5
+; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v15
+; GISEL-NEXT: v_add_i32_e32 v15, vcc, v19, v18
+; GISEL-NEXT: v_add_i32_e32 v13, vcc, v14, v13
+; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v17
; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v12, v10
-; GISEL-NEXT: v_add_i32_e32 v12, vcc, v17, v14
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v10
-; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v12
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v5
+; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v15
+; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v12, vcc, v12, v14
+; GISEL-NEXT: v_add_i32_e32 v13, vcc, v13, v15
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v12
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v13
+; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v10
; GISEL-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc
-; GISEL-NEXT: v_mul_lo_u32 v5, 0, v2
-; GISEL-NEXT: v_mul_hi_u32 v8, v6, v2
-; GISEL-NEXT: v_mul_hi_u32 v2, 0, v2
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v13
-; GISEL-NEXT: v_addc_u32_e32 v9, vcc, v11, v9, vcc
-; GISEL-NEXT: v_mul_lo_u32 v10, 0, v7
-; GISEL-NEXT: v_mul_hi_u32 v11, v0, v7
-; GISEL-NEXT: v_mul_hi_u32 v7, 0, v7
-; GISEL-NEXT: v_mul_lo_u32 v12, v6, v4
+; GISEL-NEXT: v_mul_lo_u32 v8, 0, v6
+; GISEL-NEXT: v_mul_hi_u32 v10, v0, v6
+; GISEL-NEXT: v_mul_hi_u32 v6, 0, v6
+; GISEL-NEXT: v_add_i32_e32 v5, vcc, v7, v5
+; GISEL-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc
+; GISEL-NEXT: v_mul_lo_u32 v9, 0, v5
+; GISEL-NEXT: v_mul_hi_u32 v11, v2, v5
+; GISEL-NEXT: v_mul_hi_u32 v5, 0, v5
+; GISEL-NEXT: v_mul_lo_u32 v12, v0, v4
; GISEL-NEXT: v_mul_lo_u32 v13, 0, v4
-; GISEL-NEXT: v_mul_hi_u32 v14, v6, v4
+; GISEL-NEXT: v_mul_hi_u32 v14, v0, v4
; GISEL-NEXT: v_mul_hi_u32 v4, 0, v4
-; GISEL-NEXT: v_mul_lo_u32 v17, v0, v9
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v17
+; GISEL-NEXT: v_mul_lo_u32 v15, v2, v7
+; GISEL-NEXT: v_mul_lo_u32 v17, 0, v7
+; GISEL-NEXT: v_mul_hi_u32 v18, v2, v7
+; GISEL-NEXT: v_mul_hi_u32 v7, 0, v7
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v12
+; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v6, vcc, v13, v6
+; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v15
+; GISEL-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v5, vcc, v17, v5
; GISEL-NEXT: v_cndmask_b32_e64 v17, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
-; GISEL-NEXT: v_mul_lo_u32 v10, 0, v9
-; GISEL-NEXT: v_mul_hi_u32 v11, v0, v9
-; GISEL-NEXT: v_mul_hi_u32 v9, 0, v9
-; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v12
-; GISEL-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v2, s[4:5], v13, v2
-; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v7, s[4:5], v10, v7
-; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v5, s[4:5], v5, v8
-; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5]
-; GISEL-NEXT: v_add_i32_e64 v2, s[4:5], v2, v14
-; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v11
-; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, v12, v5
-; GISEL-NEXT: v_add_i32_e32 v8, vcc, v13, v8
-; GISEL-NEXT: v_add_i32_e32 v12, vcc, v17, v14
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v5
-; GISEL-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v12
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v8, v10
+; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v14
+; GISEL-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, v9, v11
+; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v18
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, v8, v5
-; GISEL-NEXT: v_mul_lo_u32 v8, v3, v2
-; GISEL-NEXT: v_mul_lo_u32 v12, 0, v2
-; GISEL-NEXT: v_mul_hi_u32 v2, v3, v2
-; GISEL-NEXT: v_add_i32_e32 v10, vcc, v10, v11
-; GISEL-NEXT: v_mul_lo_u32 v11, v1, v7
-; GISEL-NEXT: v_mul_lo_u32 v13, 0, v7
-; GISEL-NEXT: v_mul_hi_u32 v7, v1, v7
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, v9, v10
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v12, v8
+; GISEL-NEXT: v_add_i32_e32 v10, vcc, v13, v10
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, v15, v9
+; GISEL-NEXT: v_add_i32_e32 v11, vcc, v17, v11
+; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v8
+; GISEL-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v9
+; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
+; GISEL-NEXT: v_add_i32_e32 v8, vcc, v10, v8
+; GISEL-NEXT: v_mul_lo_u32 v10, v3, v6
+; GISEL-NEXT: v_mul_lo_u32 v12, 0, v6
+; GISEL-NEXT: v_mul_hi_u32 v6, v3, v6
+; GISEL-NEXT: v_add_i32_e32 v9, vcc, v11, v9
+; GISEL-NEXT: v_mul_lo_u32 v11, v1, v5
+; GISEL-NEXT: v_mul_lo_u32 v13, 0, v5
+; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v8
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; GISEL-NEXT: v_mul_lo_u32 v4, v3, v4
-; GISEL-NEXT: v_mul_lo_u32 v5, v1, v5
+; GISEL-NEXT: v_mul_lo_u32 v7, v1, v7
; GISEL-NEXT: v_add_i32_e32 v4, vcc, v12, v4
-; GISEL-NEXT: v_add_i32_e32 v5, vcc, v13, v5
-; GISEL-NEXT: v_add_i32_e32 v2, vcc, v4, v2
-; GISEL-NEXT: v_add_i32_e32 v4, vcc, v5, v7
-; GISEL-NEXT: v_sub_i32_e32 v5, vcc, v6, v8
-; GISEL-NEXT: v_subb_u32_e64 v6, s[4:5], 0, v2, vcc
-; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], 0, v2
-; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v3
+; GISEL-NEXT: v_add_i32_e32 v7, vcc, v13, v7
+; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v6
+; GISEL-NEXT: v_add_i32_e32 v5, vcc, v7, v5
+; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v10
+; GISEL-NEXT: v_subb_u32_e64 v6, s[4:5], 0, v4, vcc
+; GISEL-NEXT: v_sub_i32_e64 v4, s[4:5], 0, v4
+; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v3
; GISEL-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
-; GISEL-NEXT: v_sub_i32_e64 v8, s[4:5], v0, v11
-; GISEL-NEXT: v_subb_u32_e64 v9, s[6:7], 0, v4, s[4:5]
-; GISEL-NEXT: v_sub_i32_e64 v0, s[6:7], 0, v4
-; GISEL-NEXT: v_cmp_ge_u32_e64 s[6:7], v8, v1
-; GISEL-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[6:7]
+; GISEL-NEXT: v_sub_i32_e64 v2, s[4:5], v2, v11
+; GISEL-NEXT: v_subb_u32_e64 v8, s[6:7], 0, v5, s[4:5]
+; GISEL-NEXT: v_sub_i32_e64 v5, s[6:7], 0, v5
+; GISEL-NEXT: v_cmp_ge_u32_e64 s[6:7], v2, v1
+; GISEL-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[6:7]
; GISEL-NEXT: v_cmp_eq_u32_e64 s[6:7], 0, v6
-; GISEL-NEXT: v_cndmask_b32_e64 v7, v15, v7, s[6:7]
-; GISEL-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v9
-; GISEL-NEXT: v_cndmask_b32_e32 v4, v16, v4, vcc
-; GISEL-NEXT: v_subbrev_u32_e64 v0, vcc, 0, v0, s[4:5]
-; GISEL-NEXT: v_sub_i32_e32 v10, vcc, v5, v3
-; GISEL-NEXT: v_subbrev_u32_e32 v2, vcc, 0, v2, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v7, v16, v7, s[6:7]
+; GISEL-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v8
+; GISEL-NEXT: v_cndmask_b32_e32 v9, v16, v9, vcc
+; GISEL-NEXT: v_subbrev_u32_e64 v5, vcc, 0, v5, s[4:5]
+; GISEL-NEXT: v_sub_i32_e32 v10, vcc, v0, v3
+; GISEL-NEXT: v_subbrev_u32_e32 v4, vcc, 0, v4, vcc
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v10, v3
; GISEL-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc
-; GISEL-NEXT: v_sub_i32_e32 v12, vcc, v8, v1
-; GISEL-NEXT: v_subbrev_u32_e32 v13, vcc, 0, v0, vcc
+; GISEL-NEXT: v_sub_i32_e32 v12, vcc, v2, v1
+; GISEL-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v5, vcc
; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v12, v1
-; GISEL-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
-; GISEL-NEXT: v_cndmask_b32_e32 v11, v19, v11, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v13, 0, -1, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4
+; GISEL-NEXT: v_cndmask_b32_e32 v11, v16, v11, vcc
; GISEL-NEXT: v_sub_i32_e32 v3, vcc, v10, v3
-; GISEL-NEXT: v_subbrev_u32_e32 v14, vcc, 0, v2, vcc
-; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v13
-; GISEL-NEXT: v_cndmask_b32_e32 v0, v18, v0, vcc
+; GISEL-NEXT: v_subbrev_u32_e32 v14, vcc, 0, v4, vcc
+; GISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
+; GISEL-NEXT: v_cndmask_b32_e32 v13, v16, v13, vcc
; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v12, v1
-; GISEL-NEXT: v_subbrev_u32_e32 v15, vcc, 0, v13, vcc
+; GISEL-NEXT: v_subbrev_u32_e32 v15, vcc, 0, v5, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11
; GISEL-NEXT: v_cndmask_b32_e32 v3, v10, v3, vcc
-; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0
+; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v13
; GISEL-NEXT: v_cndmask_b32_e64 v1, v12, v1, s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e32 v10, v2, v14, vcc
+; GISEL-NEXT: v_cndmask_b32_e32 v4, v4, v14, vcc
; GISEL-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
-; GISEL-NEXT: v_cndmask_b32_e32 v0, v5, v3, vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v3, v13, v15, s[4:5]
-; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v4
-; GISEL-NEXT: v_cndmask_b32_e64 v2, v8, v1, s[4:5]
-; GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v10, vcc
-; GISEL-NEXT: v_cndmask_b32_e64 v3, v9, v3, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v3, v5, v15, s[4:5]
+; GISEL-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v9
+; GISEL-NEXT: v_cndmask_b32_e64 v2, v2, v1, s[4:5]
+; GISEL-NEXT: v_cndmask_b32_e32 v1, v6, v4, vcc
+; GISEL-NEXT: v_cndmask_b32_e64 v3, v8, v3, s[4:5]
; GISEL-NEXT: s_setpc_b64 s[30:31]
;
; CGP-LABEL: v_urem_v2i64_24bit: