riscv: Add a SYSCON driver for SiFive's Core Local Interruptor

This adds U-Boot syscon driver for SiFive's Core Local Interruptor
(CLINT). The CLINT block holds memory-mapped control and status
registers associated with software and timer interrupts.

This driver implements the riscv_get_time() API as required by
the generic RISC-V timer driver, as well as some other APIs that
are needed for handling IPI.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 55c60e4..f513f52 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -95,4 +95,13 @@ config 32BIT
 config 64BIT
        bool
 
+config SIFIVE_CLINT
+       bool
+       depends on RISCV_MMODE
+       select REGMAP
+       select SYSCON
+       help
+         The SiFive CLINT block holds memory-mapped control and status registers
+         associated with software and timer interrupts.
+
 endmenu

diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index 4d5d623..46fcfab 100644 (file)
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -12,6 +12,9 @@
 
 /* Architecture-specific global data */
 struct arch_global_data {
+#ifdef CONFIG_SIFIVE_CLINT
+       void __iomem *clint;    /* clint base address */
+#endif
 };
 
 #include <asm-generic/global_data.h>

diff --git a/arch/riscv/include/asm/syscon.h b/arch/riscv/include/asm/syscon.h
new file mode 100644 (file)
index 0000000..d311ee6
--- /dev/null
+++ b/arch/riscv/include/asm/syscon.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#ifndef _ASM_SYSCON_H
+#define _ASM_SYSCON_H
+
+/*
+ * System controllers in a RISC-V system
+ *
+ * So far only SiFive's Core Local Interruptor (CLINT) is defined.
+ */
+enum {
+       RISCV_NONE,
+       RISCV_SYSCON_CLINT,     /* Core Local Interruptor (CLINT) */
+};
+
+#endif /* _ASM_SYSCON_H */

diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index b58db89..b13c876 100644 (file)
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -9,6 +9,7 @@
 obj-$(CONFIG_CMD_BOOTM) += bootm.o
 obj-$(CONFIG_CMD_GO) += boot.o
 obj-y  += cache.o
+obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
 obj-y  += interrupts.o
 obj-y  += reset.o
 obj-y   += setjmp.o

diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c
new file mode 100644 (file)
index 0000000..d24e0d5
--- /dev/null
+++ b/arch/riscv/lib/sifive_clint.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT).
+ * The CLINT block holds memory-mapped control and status registers
+ * associated with software and timer interrupts.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <regmap.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/syscon.h>
+
+/* MSIP registers */
+#define MSIP_REG(base, hart)           ((ulong)(base) + (hart) * 4)
+/* mtime compare register */
+#define MTIMECMP_REG(base, hart)       ((ulong)(base) + 0x4000 + (hart) * 8)
+/* mtime register */
+#define MTIME_REG(base)                        ((ulong)(base) + 0xbff8)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CLINT_BASE_GET(void)                                           \
+       do {                                                            \
+               long *ret;                                              \
+                                                                       \
+               if (!gd->arch.clint) {                                  \
+                       ret = syscon_get_first_range(RISCV_SYSCON_CLINT); \
+                       if (IS_ERR(ret))                                \
+                               return PTR_ERR(ret);                    \
+                       gd->arch.clint = ret;                           \
+               }                                                       \
+       } while (0)
+
+int riscv_get_time(u64 *time)
+{
+       CLINT_BASE_GET();
+
+       *time = readq((void __iomem *)MTIME_REG(gd->arch.clint));
+
+       return 0;
+}
+
+int riscv_set_timecmp(int hart, u64 cmp)
+{
+       CLINT_BASE_GET();
+
+       writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart));
+
+       return 0;
+}
+
+int riscv_send_ipi(int hart)
+{
+       CLINT_BASE_GET();
+
+       writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
+
+       return 0;
+}
+
+int riscv_clear_ipi(int hart)
+{
+       CLINT_BASE_GET();
+
+       writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
+
+       return 0;
+}
+
+static const struct udevice_id sifive_clint_ids[] = {
+       { .compatible = "riscv,clint0", .data = RISCV_SYSCON_CLINT },
+       { }
+};
+
+U_BOOT_DRIVER(sifive_clint) = {
+       .name           = "sifive_clint",
+       .id             = UCLASS_SYSCON,
+       .of_match       = sifive_clint_ids,
+       .flags          = DM_FLAG_PRE_RELOC,
+};