def WFIT : RegInputSystemI<0b0000, 0b001, "wfit">;
}
+// Branch Record Buffer two-word mnemonic instructions
+class BRBEI<bits<3> op2, string keyword>
+ : SimpleSystemI<0, (ins), "brb", keyword>, Sched<[WriteSys]> {
+ let Inst{31-8} = 0b110101010000100101110010;
+ let Inst{7-5} = op2;
+ let Predicates = [HasBRBE];
}
+def BRB_IALL: BRBEI<0b100, "\tiall">;
+def BRB_INJ: BRBEI<0b101, "\tinj">;
+
+}
+
+// Allow uppercase and lowercase keyword arguments for BRB IALL and BRB INJ
+def : TokenAlias<"INJ", "inj">;
+def : TokenAlias<"IALL", "iall">;
// ARMv8.2-A Dot Product
let Predicates = [HasDotProd] in {
bool parseSymbolicImmVal(const MCExpr *&ImmVal);
bool parseNeonVectorList(OperandVector &Operands);
bool parseOptionalMulOperand(OperandVector &Operands);
+ bool parseKeywordOperand(OperandVector &Operands);
bool parseOperand(OperandVector &Operands, bool isCondCode,
bool invertCondCode);
bool parseImmExpr(int64_t &Out);
return Error(getLoc(), "expected 'vl' or '#<imm>'");
}
+bool AArch64AsmParser::parseKeywordOperand(OperandVector &Operands) {
+ MCAsmParser &Parser = getParser();
+ auto Tok = Parser.getTok();
+ if (Tok.isNot(AsmToken::Identifier))
+ return true;
+ Operands.push_back(AArch64Operand::CreateToken(Tok.getString(), false,
+ Tok.getLoc(), getContext()));
+ Parser.Lex();
+ return false;
+}
+
/// parseOperand - Parse a arm instruction operand. For now this parses the
/// operand regardless of the mnemonic.
bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
if (GotShift != MatchOperand_NoMatch)
return GotShift;
+ // If this is a two-word mnemonic, parse its special keyword
+ // operand as an identifier.
+ if (Mnemonic == "brb")
+ return parseKeywordOperand(Operands);
+
// This was not a register so parse other operands that start with an
// identifier (like labels) as expressions and create them as immediates.
const MCExpr *IdVal;
// CHECK: mrs x5, BRBTGT31_EL1 // encoding: [0xc5,0x8f,0x31,0xd5]
// ERROR-NO-BRBE: [[@LINE-4]]:5: error: expected writable system register
// ERROR-NO-BRBE: [[@LINE-4]]:9: error: expected readable system register
+
+brb iall
+brb inj
+// CHECK: brb iall // encoding: [0x9f,0x72,0x09,0xd5]
+// CHECK: brb inj // encoding: [0xbf,0x72,0x09,0xd5]
+// ERROR-NO-BRBE: [[@LINE-4]]:1: error: instruction requires: brbe
+// ERROR-NO-BRBE: [[@LINE-4]]:1: error: instruction requires: brbe
+
+brb IALL
+brb INJ
+// CHECK: brb iall // encoding: [0x9f,0x72,0x09,0xd5]
+// CHECK: brb inj // encoding: [0xbf,0x72,0x09,0xd5]
+// ERROR-NO-BRBE: [[@LINE-4]]:1: error: instruction requires: brbe
+// ERROR-NO-BRBE: [[@LINE-4]]:1: error: instruction requires: brbe