riscv: dts: Change cpu vdd per stress test

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index f1def08..b816b2c 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -22,19 +22,19 @@
                        opp-shared;
                        opp-375000000 {
                                        opp-hz = /bits/ 64 <375000000>;
-                                       opp-microvolt = <880000>;
+                                       opp-microvolt = <800000>;
                        };
                        opp-500000000 {
                                        opp-hz = /bits/ 64 <500000000>;
-                                       opp-microvolt = <880000>;
+                                       opp-microvolt = <800000>;
                        };
                        opp-750000000 {
                                        opp-hz = /bits/ 64 <750000000>;
-                                       opp-microvolt = <880000>;
+                                       opp-microvolt = <800000>;
                        };
                        opp-1500000000 {
                                        opp-hz = /bits/ 64 <1500000000>;
-                                       opp-microvolt = <1000000>;
+                                       opp-microvolt = <1040000>;
                        };
        };