s5pc100: universal: Fix OneNAND clock initialization on s5pc110

Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>

diff --git a/board/samsung/universal/onenand.c b/board/samsung/universal/onenand.c
index 97a0532..1a36a68 100644 (file)
--- a/board/samsung/universal/onenand.c
+++ b/board/samsung/universal/onenand.c
@@ -19,12 +19,12 @@ extern void s3c_onenand_init(struct mtd_info *);
 
 static inline int onenand_read_reg(int offset)
 {
-       return readl(CONFIG_SYS_ONENAND_BASE + offset);
+       return readl(S5PC100_ONENAND_BASE + offset);
 }
 
 static inline void onenand_write_reg(int value, int offset)
 {
-       writel(value, CONFIG_SYS_ONENAND_BASE + offset);
+       writel(value, S5PC100_ONENAND_BASE + offset);
 }
 
 static int s5pc1xx_clock_read(int offset)
@@ -42,43 +42,42 @@ void onenand_board_init(struct mtd_info *mtd)
        struct onenand_chip *this = mtd->priv;
        int value;
 
-       this->base = (void *)CONFIG_SYS_ONENAND_BASE;
-
-       if (cpu_is_s5pc110())
-               this->base = (void *)0xB0000000;
-
-       /* D0 Domain system 1 clock gating */
-       value = s5pc1xx_clock_read(S5P_CLK_GATE_D00_OFFSET);
-       value &= ~(1 << 2);             /* CFCON */
-       value |= (1 << 2);
-       s5pc1xx_clock_write(value, S5P_CLK_GATE_D00_OFFSET);
-
-       /* D0 Domain memory clock gating */
-       value = s5pc1xx_clock_read(S5P_CLK_GATE_D01_OFFSET);
-       value &= ~(1 << 2);             /* CLK_ONENANDC */
-       value |= (1 << 2);
-       s5pc1xx_clock_write(value, S5P_CLK_GATE_D01_OFFSET);
-
-       /* System Special clock gating */
-       value = s5pc1xx_clock_read(S5P_CLK_GATE_SCLK0_OFFSET);
-       value &= ~(1 << 2);             /* OneNAND */
-       value |= (1 << 2);
-       s5pc1xx_clock_write(value, S5P_CLK_GATE_SCLK0_OFFSET);
-
-       value = s5pc1xx_clock_read(S5P_CLK_SRC0_OFFSET);
-       value &= ~(1 << 24);            /* MUX_1nand: 0 from HCLKD0 */
-//     value |= (1 << 24);             /* MUX_1nand: 1 from DIV_D1_BUS */
-       value &= ~(1 << 20);            /* MUX_HREF: 0 from FIN_27M */
-       s5pc1xx_clock_write(value, S5P_CLK_SRC0_OFFSET);
-
-       value = s5pc1xx_clock_read(S5P_CLK_DIV1_OFFSET);
-//     value &= ~(3 << 20);            /* DIV_1nand: 1 / (ratio+1) */
-//     value |= (0 << 20);             /* ratio = 1 */
-       value &= ~(3 << 16);
-       value |= (1 << 16);
-       s5pc1xx_clock_write(value, S5P_CLK_DIV1_OFFSET);
-
-       if (cpu_is_s5pc100()) {
+       if (cpu_is_s5pc110()) {
+               this->base = (void *) 0xB0000000;
+       } else {
+               this->base = (void *) S5PC100_ONENAND_BASE;
+
+               /* D0 Domain system 1 clock gating */
+               value = s5pc1xx_clock_read(S5P_CLK_GATE_D00_OFFSET);
+               value &= ~(1 << 2);             /* CFCON */
+               value |= (1 << 2);
+               s5pc1xx_clock_write(value, S5P_CLK_GATE_D00_OFFSET);
+
+               /* D0 Domain memory clock gating */
+               value = s5pc1xx_clock_read(S5P_CLK_GATE_D01_OFFSET);
+               value &= ~(1 << 2);             /* CLK_ONENANDC */
+               value |= (1 << 2);
+               s5pc1xx_clock_write(value, S5P_CLK_GATE_D01_OFFSET);
+
+               /* System Special clock gating */
+               value = s5pc1xx_clock_read(S5P_CLK_GATE_SCLK0_OFFSET);
+               value &= ~(1 << 2);             /* OneNAND */
+               value |= (1 << 2);
+               s5pc1xx_clock_write(value, S5P_CLK_GATE_SCLK0_OFFSET);
+
+               value = s5pc1xx_clock_read(S5P_CLK_SRC0_OFFSET);
+               value &= ~(1 << 24);            /* MUX_1nand: 0 from HCLKD0 */
+       //      value |= (1 << 24);             /* MUX_1nand: 1 from DIV_D1_BUS */
+               value &= ~(1 << 20);            /* MUX_HREF: 0 from FIN_27M */
+               s5pc1xx_clock_write(value, S5P_CLK_SRC0_OFFSET);
+
+               value = s5pc1xx_clock_read(S5P_CLK_DIV1_OFFSET);
+       //      value &= ~(3 << 20);            /* DIV_1nand: 1 / (ratio+1) */
+       //      value |= (0 << 20);             /* ratio = 1 */
+               value &= ~(3 << 16);
+               value |= (1 << 16);
+               s5pc1xx_clock_write(value, S5P_CLK_DIV1_OFFSET);
+
                onenand_write_reg(ONENAND_MEM_RESET_COLD, MEM_RESET_OFFSET);
 
                while (!(onenand_read_reg(INT_ERR_STAT_OFFSET) & RST_CMP))
@@ -95,20 +94,6 @@ void onenand_board_init(struct mtd_info *mtd)
                value &= ~RDY_ACT;
                onenand_write_reg(value, INT_ERR_MASK_OFFSET);
 
-#if 0
-               MEM_CFG0_REG |=
-                       ONENAND_SYS_CFG1_SYNC_READ |
-                       ONENAND_SYS_CFG1_BRL_4 |
-                       ONENAND_SYS_CFG1_BL_16 |
-                       ONENAND_SYS_CFG1_RDY |
-                       ONENAND_SYS_CFG1_INT |
-                       ONENAND_SYS_CFG1_IOBE
-                       ;
-               MEM_CFG0_REG |= ONENAND_SYS_CFG1_RDY;
-               MEM_CFG0_REG |= ONENAND_SYS_CFG1_INT; 
-               MEM_CFG0_REG |= ONENAND_SYS_CFG1_IOBE;
-#endif
-
                s3c_onenand_init(mtd);
        }
 }

diff --git a/include/asm-arm/arch-s5pc1xx/clock.h b/include/asm-arm/arch-s5pc1xx/clock.h
index 94b0662..f477db1 100644 (file)
--- a/include/asm-arm/arch-s5pc1xx/clock.h
+++ b/include/asm-arm/arch-s5pc1xx/clock.h
@@ -27,7 +27,6 @@
 /*
  * Clock control
  */
-#define S5P_CLOCK_BASE                 S5P_PA_CLK
 
 /* Clock Register */
 #define S5PC100_APLL_LOCK_OFFSET       0x0

diff --git a/include/asm-arm/arch-s5pc1xx/cpu.h b/include/asm-arm/arch-s5pc1xx/cpu.h
index e829fae..0b6e162 100644 (file)
--- a/include/asm-arm/arch-s5pc1xx/cpu.h
+++ b/include/asm-arm/arch-s5pc1xx/cpu.h
@@ -37,6 +37,7 @@
 #define S5PC100_VIC1_BASE      0xE4100000
 #define S5PC100_VIC2_BASE      0xE4200000
 #define S5PC100_SROMC_BASE     0xE7000000
+#define S5PC100_ONENAND_BASE   0xE7100000
 #define S5PC100_WATCHDOG_BASE  0xEA200000
 
 #define S5PC110_WATCHDOG_BASE  0xE2700000