net/mlx5: Add MEMIC operations related bits
authorMaor Gottlieb <maorg@nvidia.com>
Sun, 11 Apr 2021 12:29:18 +0000 (15:29 +0300)
committerLeon Romanovsky <leonro@nvidia.com>
Tue, 13 Apr 2021 19:18:54 +0000 (22:18 +0300)
Add the MEMIC operations bits and structures to the mlx5_ifc file.

Signed-off-by: Maor Gottlieb <maorg@nvidia.com>
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
include/linux/mlx5/mlx5_ifc.h

index 432290b..47241eb 100644 (file)
@@ -133,6 +133,7 @@ enum {
        MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
        MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
        MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
+       MLX5_CMD_OP_MODIFY_MEMIC                  = 0x207,
        MLX5_CMD_OP_CREATE_EQ                     = 0x301,
        MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
        MLX5_CMD_OP_QUERY_EQ                      = 0x303,
@@ -1017,7 +1018,11 @@ struct mlx5_ifc_device_mem_cap_bits {
 
        u8         header_modify_sw_icm_start_address[0x40];
 
-       u8         reserved_at_180[0x680];
+       u8         reserved_at_180[0x80];
+
+       u8         memic_operations[0x20];
+
+       u8         reserved_at_220[0x5e0];
 };
 
 struct mlx5_ifc_device_event_cap_bits {
@@ -10417,6 +10422,41 @@ struct mlx5_ifc_destroy_vport_lag_in_bits {
        u8         reserved_at_40[0x40];
 };
 
+enum {
+       MLX5_MODIFY_MEMIC_OP_MOD_ALLOC,
+       MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC,
+};
+
+struct mlx5_ifc_modify_memic_in_bits {
+       u8         opcode[0x10];
+       u8         uid[0x10];
+
+       u8         reserved_at_20[0x10];
+       u8         op_mod[0x10];
+
+       u8         reserved_at_40[0x20];
+
+       u8         reserved_at_60[0x18];
+       u8         memic_operation_type[0x8];
+
+       u8         memic_start_addr[0x40];
+
+       u8         reserved_at_c0[0x140];
+};
+
+struct mlx5_ifc_modify_memic_out_bits {
+       u8         status[0x8];
+       u8         reserved_at_8[0x18];
+
+       u8         syndrome[0x20];
+
+       u8         reserved_at_40[0x40];
+
+       u8         memic_operation_addr[0x40];
+
+       u8         reserved_at_c0[0x140];
+};
+
 struct mlx5_ifc_alloc_memic_in_bits {
        u8         opcode[0x10];
        u8         reserved_at_10[0x10];