#if defined(__i386__)
#define AREG0 "ebp"
-#define AREG1 "ebx"
-#define AREG2 "esi"
#elif defined(__x86_64__)
#define AREG0 "r14"
-#define AREG1 "r15"
-#define AREG2 "r12"
#elif defined(_ARCH_PPC)
#define AREG0 "r27"
-#define AREG1 "r24"
-#define AREG2 "r25"
#elif defined(__arm__)
#define AREG0 "r7"
-#define AREG1 "r4"
-#define AREG2 "r5"
#elif defined(__hppa__)
#define AREG0 "r17"
-#define AREG1 "r14"
-#define AREG2 "r15"
#elif defined(__mips__)
#define AREG0 "fp"
-#define AREG1 "s0"
-#define AREG2 "s1"
#elif defined(__sparc__)
#ifdef CONFIG_SOLARIS
#define AREG0 "g2"
-#define AREG1 "g3"
-#define AREG2 "g4"
#else
#ifdef __sparc_v9__
#define AREG0 "g5"
-#define AREG1 "g6"
-#define AREG2 "g7"
#else
#define AREG0 "g6"
-#define AREG1 "g1"
-#define AREG2 "g2"
#endif
#endif
#elif defined(__s390__)
#define AREG0 "r10"
-#define AREG1 "r7"
-#define AREG2 "r8"
#elif defined(__alpha__)
/* Note $15 is the frame pointer, so anything in op-i386.c that would
require a frame pointer, like alloca, would probably loose. */
#define AREG0 "$15"
-#define AREG1 "$9"
-#define AREG2 "$10"
#elif defined(__mc68000)
#define AREG0 "%a5"
-#define AREG1 "%a4"
-#define AREG2 "%d7"
#elif defined(__ia64__)
#define AREG0 "r7"
-#define AREG1 "r4"
-#define AREG2 "r5"
#else
#error unsupported CPU
#endif
enum {
/* Note: must be synced with dyngen-exec.h */
TCG_AREG0 = TCG_REG_R7,
- TCG_AREG1 = TCG_REG_R4,
- TCG_AREG2 = TCG_REG_R5,
};
static inline void flush_icache_range(unsigned long start, unsigned long stop)
/* Note: must be synced with dyngen-exec.h */
#define TCG_AREG0 TCG_REG_R17
-#define TCG_AREG1 TCG_REG_R14
-#define TCG_AREG2 TCG_REG_R15
static inline void flush_icache_range(unsigned long start, unsigned long stop)
{
/* Note: must be synced with dyngen-exec.h */
#define TCG_AREG0 TCG_REG_EBP
-#define TCG_AREG1 TCG_REG_EBX
-#define TCG_AREG2 TCG_REG_ESI
static inline void flush_icache_range(unsigned long start, unsigned long stop)
{
/* Note: must be synced with dyngen-exec.h */
#define TCG_AREG0 TCG_REG_FP
-#define TCG_AREG1 TCG_REG_S0
-#define TCG_AREG2 TCG_REG_S1
#include <sys/cachectl.h>
#define TCG_TARGET_HAS_orc_i32
#define TCG_AREG0 TCG_REG_R27
-#define TCG_AREG1 TCG_REG_R24
-#define TCG_AREG2 TCG_REG_R25
#define TCG_TARGET_HAS_GUEST_BASE
/* #define TCG_TARGET_HAS_orc_i64 */
#define TCG_AREG0 TCG_REG_R27
-#define TCG_AREG1 TCG_REG_R24
-#define TCG_AREG2 TCG_REG_R25
#define TCG_TARGET_HAS_GUEST_BASE
enum {
/* Note: must be synced with dyngen-exec.h */
TCG_AREG0 = TCG_REG_R10,
- TCG_AREG1 = TCG_REG_R7,
- TCG_AREG2 = TCG_REG_R8,
- TCG_AREG3 = TCG_REG_R9,
};
static inline void flush_icache_range(unsigned long start, unsigned long stop)
#define TCG_TARGET_HAS_orc_i64
#endif
-/* Note: must be synced with dyngen-exec.h and Makefile.target */
+/* Note: must be synced with dyngen-exec.h */
#ifdef CONFIG_SOLARIS
#define TCG_AREG0 TCG_REG_G2
-#define TCG_AREG1 TCG_REG_G3
-#define TCG_AREG2 TCG_REG_G4
#elif defined(__sparc_v9__)
#define TCG_AREG0 TCG_REG_G5
-#define TCG_AREG1 TCG_REG_G6
-#define TCG_AREG2 TCG_REG_G7
#else
#define TCG_AREG0 TCG_REG_G6
-#define TCG_AREG1 TCG_REG_G1
-#define TCG_AREG2 TCG_REG_G2
#endif
static inline void flush_icache_range(unsigned long start, unsigned long stop)
/* Note: must be synced with dyngen-exec.h */
#define TCG_AREG0 TCG_REG_R14
-#define TCG_AREG1 TCG_REG_R15
-#define TCG_AREG2 TCG_REG_R12
static inline void flush_icache_range(unsigned long start, unsigned long stop)
{