net: mvpp2: set xlg flow control in mvpp2_mac_link_up()

Set the flow control settings in mvpp2_mac_link_up() for 10G links
just as we do for 1G and slower links. This is now the preferred
location.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index 06e160a..212fc3b 100644 (file)
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -4959,17 +4959,9 @@ static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode,
 {
        u32 val;
 
-       val = MVPP22_XLG_CTRL0_MAC_RESET_DIS;
-       if (state->pause & MLO_PAUSE_TX)
-               val |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
-
-       if (state->pause & MLO_PAUSE_RX)
-               val |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
-
        mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
-                    MVPP22_XLG_CTRL0_MAC_RESET_DIS |
-                    MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN |
-                    MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN, val);
+                    MVPP22_XLG_CTRL0_MAC_RESET_DIS,
+                    MVPP22_XLG_CTRL0_MAC_RESET_DIS);
        mvpp2_modify(port->base + MVPP22_XLG_CTRL4_REG,
                     MVPP22_XLG_CTRL4_MACMODSELECT_GMAC |
                     MVPP22_XLG_CTRL4_EN_IDLE_CHECK |
@@ -5159,10 +5151,17 @@ static void mvpp2_mac_link_up(struct phylink_config *config,
 
        if (mvpp2_is_xlg(interface)) {
                if (!phylink_autoneg_inband(mode)) {
+                       val = MVPP22_XLG_CTRL0_FORCE_LINK_PASS;
+                       if (tx_pause)
+                               val |= MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN;
+                       if (rx_pause)
+                               val |= MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN;
+
                        mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG,
                                     MVPP22_XLG_CTRL0_FORCE_LINK_DOWN |
-                                    MVPP22_XLG_CTRL0_FORCE_LINK_PASS,
-                                    MVPP22_XLG_CTRL0_FORCE_LINK_PASS);
+                                    MVPP22_XLG_CTRL0_FORCE_LINK_PASS |
+                                    MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN |
+                                    MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN, val);
                }
        } else {
                if (!phylink_autoneg_inband(mode)) {