lavapipe: add loop unrolling.
authorDave Airlie <airlied@redhat.com>
Tue, 8 Mar 2022 08:31:13 +0000 (18:31 +1000)
committerMarge Bot <emma+marge@anholt.net>
Wed, 30 Mar 2022 02:16:18 +0000 (02:16 +0000)
zink was giving us rolled spir-v and nothing was unrolling it,
start unrolling the NIR in the frontend.

unrolling would leave a texture with a constant texture_offset,
translate it to a texture index.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15287>

src/gallium/drivers/zink/ci/zink-lvp-fails.txt
src/gallium/frontends/lavapipe/lvp_pipeline.c

index 21cf96c..91f9ee9 100644 (file)
@@ -328,13 +328,6 @@ spec@!opengl 3.0@clearbuffer-depth-cs-probe,Fail
 spec@arb_post_depth_coverage@arb_post_depth_coverage-multisampling,Fail
 spec@arb_shader_image_load_store@early-z,Fail
 spec@arb_shader_image_load_store@early-z@occlusion query test/early-z pass,Fail
-spec@arb_shader_image_load_store@indexing,Fail
-spec@arb_shader_image_load_store@indexing@Compute shader/dynamically uniform indexing test,Fail
-spec@arb_shader_image_load_store@indexing@Fragment shader/dynamically uniform indexing test,Fail
-spec@arb_shader_image_load_store@indexing@Geometry shader/dynamically uniform indexing test,Fail
-spec@arb_shader_image_load_store@indexing@Tessellation control shader/dynamically uniform indexing test,Fail
-spec@arb_shader_image_load_store@indexing@Tessellation evaluation shader/dynamically uniform indexing test,Fail
-spec@arb_shader_image_load_store@indexing@Vertex shader/dynamically uniform indexing test,Fail
 spec@arb_shader_image_load_store@invalid,Fail
 spec@arb_shader_image_load_store@invalid@imageLoad/incompatible format test/imageBuffer,Fail
 spec@khr_texture_compression_astc@array-gles,Fail
index 9a555b4..247a898 100644 (file)
@@ -719,6 +719,39 @@ lower_demote(nir_shader *nir)
    return nir_shader_instructions_pass(nir, lower_demote_impl, nir_metadata_dominance, NULL);
 }
 
+static bool
+find_tex(const nir_instr *instr, const void *data_cb)
+{
+   if (instr->type == nir_instr_type_tex)
+      return true;
+   return false;
+}
+
+static nir_ssa_def *
+fixup_tex_instr(struct nir_builder *b, nir_instr *instr, void *data_cb)
+{
+   nir_tex_instr *tex_instr = nir_instr_as_tex(instr);
+   unsigned offset = 0;
+
+   int idx = nir_tex_instr_src_index(tex_instr, nir_tex_src_texture_offset);
+   if (idx == -1)
+      return NULL;
+
+   if (!nir_src_is_const(tex_instr->src[idx].src))
+      return NULL;
+   offset = nir_src_comp_as_uint(tex_instr->src[idx].src, 0);
+
+   nir_tex_instr_remove_src(tex_instr, idx);
+   tex_instr->texture_index += offset;
+   return NIR_LOWER_INSTR_PROGRESS;
+}
+
+static bool
+lvp_nir_fixup_indirect_tex(nir_shader *shader)
+{
+   return nir_shader_lower_instructions(shader, find_tex, fixup_tex_instr, NULL);
+}
+
 static void
 optimize(nir_shader *nir)
 {
@@ -763,6 +796,8 @@ optimize(nir_shader *nir)
 
       NIR_PASS(progress, nir, nir_opt_deref);
       NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
+      NIR_PASS(progress, nir, nir_opt_loop_unroll);
+      NIR_PASS(progress, nir, lvp_nir_fixup_indirect_tex);
    } while (progress);
 }