uint64_t size;
/* MSAA images do not support mipmap levels. */
- assert(range->baseMipLevel == 0 && radv_get_levelCount(image, range) == 1);
+ assert(range->baseMipLevel == 0 && vk_image_subresource_level_count(&image->vk, range) == 1);
offset += slice_size * range->baseArrayLayer;
size = slice_size * vk_image_subresource_layer_count(&image->vk, range);
radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
const VkImageSubresourceRange *range, uint32_t value)
{
- uint32_t level_count = radv_get_levelCount(image, range);
+ uint32_t level_count = vk_image_subresource_level_count(&image->vk, range);
uint32_t layer_count = vk_image_subresource_layer_count(&image->vk, range);
uint32_t flush_bits = 0;
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
pipeline);
- for (uint32_t l = 0; l < radv_get_levelCount(image, range); l++) {
+ for (uint32_t l = 0; l < vk_image_subresource_level_count(&image->vk, range); l++) {
uint32_t width, height;
/* Do not write the clear color value for levels without DCC. */
radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *image,
const VkImageSubresourceRange *range, uint32_t value)
{
- uint32_t level_count = radv_get_levelCount(image, range);
+ uint32_t level_count = vk_image_subresource_level_count(&image->vk, range);
uint32_t flush_bits = 0;
uint32_t htile_mask;
{
.aspectMask = range->aspectMask,
.baseMipLevel = range->baseMipLevel,
- .levelCount = radv_get_levelCount(image, range),
+ .levelCount = vk_image_subresource_level_count(&image->vk, range),
.baseArrayLayer = range->baseArrayLayer,
.layerCount = vk_image_subresource_layer_count(&image->vk, range),
},
continue;
}
- for (uint32_t l = 0; l < radv_get_levelCount(image, range); ++l) {
+ for (uint32_t l = 0; l < vk_image_subresource_level_count(&image->vk, range); ++l) {
const uint32_t layer_count = image->vk.image_type == VK_IMAGE_TYPE_3D
? radv_minify(image->info.depth, range->baseMipLevel + l)
: vk_image_subresource_layer_count(&image->vk, range);
});
}
- for (uint32_t l = 0; l < radv_get_levelCount(image, subresourceRange); ++l) {
+ for (uint32_t l = 0; l < vk_image_subresource_level_count(&image->vk, subresourceRange); ++l) {
/* Do not decompress levels without HTILE. */
if (!radv_htile_enabled(image, subresourceRange->baseMipLevel + l))
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
device->meta_state.expand_depth_stencil_compute_pipeline);
- for (uint32_t l = 0; l < radv_get_levelCount(image, subresourceRange); l++) {
+ for (uint32_t l = 0; l < vk_image_subresource_level_count(&image->vk, subresourceRange); l++) {
uint32_t width, height;
/* Do not decompress levels without HTILE. */
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_GRAPHICS,
*pipeline);
- for (uint32_t l = 0; l < radv_get_levelCount(image, subresourceRange); ++l) {
+ for (uint32_t l = 0; l < vk_image_subresource_level_count(&image->vk, subresourceRange); ++l) {
uint32_t width, height;
/* Do not decompress levels without DCC. */
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
device->meta_state.fast_clear_flush.dcc_decompress_compute_pipeline);
- for (uint32_t l = 0; l < radv_get_levelCount(image, subresourceRange); l++) {
+ for (uint32_t l = 0; l < vk_image_subresource_level_count(&image->vk, subresourceRange); l++) {
uint32_t width, height;
/* Do not decompress levels without DCC. */
VkClearDepthStencilValue ds_clear_value, VkImageAspectFlags aspects)
{
struct radeon_cmdbuf *cs = cmd_buffer->cs;
- uint32_t level_count = radv_get_levelCount(image, range);
+ uint32_t level_count = vk_image_subresource_level_count(&image->vk, range);
if (aspects == (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
uint64_t va = radv_get_ds_clear_value_va(image, range->baseMipLevel);
return;
uint64_t va = radv_get_tc_compat_zrange_va(image, range->baseMipLevel);
- uint32_t level_count = radv_get_levelCount(image, range);
+ uint32_t level_count = vk_image_subresource_level_count(&image->vk, range);
radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));
radeon_emit(cs, S_370_DST_SEL(V_370_MEM) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(V_370_PFP));
uint64_t pred_val = value;
uint64_t va = radv_image_get_fce_pred_va(image, range->baseMipLevel);
- uint32_t level_count = radv_get_levelCount(image, range);
+ uint32_t level_count = vk_image_subresource_level_count(&image->vk, range);
uint32_t count = 2 * level_count;
ASSERTED unsigned cdw_max =
uint64_t pred_val = value;
uint64_t va = radv_image_get_dcc_pred_va(image, range->baseMipLevel);
- uint32_t level_count = radv_get_levelCount(image, range);
+ uint32_t level_count = vk_image_subresource_level_count(&image->vk, range);
uint32_t count = 2 * level_count;
assert(radv_dcc_enabled(image, range->baseMipLevel));
const VkImageSubresourceRange *range, uint32_t color_values[2])
{
struct radeon_cmdbuf *cs = cmd_buffer->cs;
- uint32_t level_count = radv_get_levelCount(image, range);
+ uint32_t level_count = vk_image_subresource_level_count(&image->vk, range);
uint32_t count = 2 * level_count;
assert(radv_image_has_cmask(image) || radv_dcc_enabled(image, range->baseMipLevel));
enum radv_queue_family family,
enum radv_queue_family queue_family);
-static inline uint32_t
-radv_get_levelCount(const struct radv_image *image, const VkImageSubresourceRange *range)
-{
- return range->levelCount == VK_REMAINING_MIP_LEVELS ? image->info.levels - range->baseMipLevel
- : range->levelCount;
-}
-
bool radv_image_is_renderable(struct radv_device *device, struct radv_image *image);
struct radeon_bo_metadata;