dt-bindings: Add headers for Host1x and VIC on Tegra234

Add clock, memory controller, powergate and reset dt-binding headers
for Host1x and VIC on Tegra234.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h
index bab85d9ba8cd965ef6bc2c90128fd99e15cb0bb5..173364a93381ad992a58f2043afad52b5e6e8a00 100644 (file)
--- a/include/dt-bindings/clock/tegra234-clock.h
+++ b/include/dt-bindings/clock/tegra234-clock.h
@@ -38,6 +38,8 @@
  * throughput and memory controller power.
  */
 #define TEGRA234_CLK_EMC                       31U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */
+#define TEGRA234_CLK_HOST1X                     46U
 /** @brief output of gate CLK_ENB_FUSE */
 #define TEGRA234_CLK_FUSE                      40U
 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */
@@ -132,6 +134,8 @@
 #define TEGRA234_CLK_UARTA                     155U
 /** @brief output of gate CLK_ENB_PEX1_CORE_6 */
 #define TEGRA234_CLK_PEX1_C6_CORE              161U
+/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */
+#define TEGRA234_CLK_VIC                        167U
 /** @brief output of gate CLK_ENB_PEX2_CORE_7 */
 #define TEGRA234_CLK_PEX2_C7_CORE              171U
 /** @brief output of gate CLK_ENB_PEX2_CORE_8 */

diff --git a/include/dt-bindings/memory/tegra234-mc.h b/include/dt-bindings/memory/tegra234-mc.h
index 8b0ddcb715ffd80768ae40e146b74dd03a3e64af..62987b47ce81c150847b4ddf60bc36713b7b8182 100644 (file)
--- a/include/dt-bindings/memory/tegra234-mc.h
+++ b/include/dt-bindings/memory/tegra234-mc.h
@@ -31,6 +31,8 @@
 #define TEGRA234_SID_PCIE8     0x09
 #define TEGRA234_SID_PCIE10    0x0b
 #define TEGRA234_SID_BPMP      0x10
+#define TEGRA234_SID_HOST1X    0x27
+#define TEGRA234_SID_VIC       0x34
 
 /*
  * memory client IDs
@@ -38,6 +40,7 @@
 
 /* High-definition audio (HDA) read clients */
 #define TEGRA234_MEMORY_CLIENT_HDAR 0x15
+#define TEGRA234_MEMORY_CLIENT_HOST1XDMAR 0x16
 /* PCIE6 read clients */
 #define TEGRA234_MEMORY_CLIENT_PCIE6AR 0x28
 /* PCIE6 write clients */
@@ -86,6 +89,8 @@
 #define TEGRA234_MEMORY_CLIENT_MGBEDWR 0x65
 /* sdmmcd memory write client */
 #define TEGRA234_MEMORY_CLIENT_SDMMCWAB 0x67
+#define TEGRA234_MEMORY_CLIENT_VICSRD 0x6c
+#define TEGRA234_MEMORY_CLIENT_VICSWR 0x6d
 /* BPMP read client */
 #define TEGRA234_MEMORY_CLIENT_BPMPR 0x93
 /* BPMP write client */

diff --git a/include/dt-bindings/power/tegra234-powergate.h b/include/dt-bindings/power/tegra234-powergate.h
index df1d4dd8dcf38ffc5dfda1bac8812c53dd63300f..ae9286cef85c7268b48e409937d4b784a908045b 100644 (file)
--- a/include/dt-bindings/power/tegra234-powergate.h
+++ b/include/dt-bindings/power/tegra234-powergate.h
@@ -19,5 +19,6 @@
 #define TEGRA234_POWER_DOMAIN_MGBEB    18U
 #define TEGRA234_POWER_DOMAIN_MGBEC    19U
 #define TEGRA234_POWER_DOMAIN_MGBED    20U
+#define TEGRA234_POWER_DOMAIN_VIC      29U
 
 #endif

diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h
index bd58a05f1d94c6c71f01b23aabcb285fbe9a6b70..d48d22b2bc7fd8361c8ae69a021c526bba2b1d40 100644 (file)
--- a/include/dt-bindings/reset/tegra234-reset.h
+++ b/include/dt-bindings/reset/tegra234-reset.h
@@ -53,6 +53,7 @@
 #define TEGRA234_RESET_MGBE3_PCS               87U
 #define TEGRA234_RESET_MGBE3_MAC               88U
 #define TEGRA234_RESET_UARTA                   100U
+#define TEGRA234_RESET_VIC                      113U
 #define TEGRA234_RESET_PEX0_CORE_0             116U
 #define TEGRA234_RESET_PEX0_CORE_1             117U
 #define TEGRA234_RESET_PEX0_CORE_2             118U