int sbi_hart_init(struct sbi_scratch *scratch, u32 hartid, bool cold_boot);
-extern void (*sbi_hart_unpriv_trap)(void);
-static inline ulong sbi_hart_unpriv_trap_addr(void)
+extern void (*sbi_hart_expected_trap)(void);
+static inline ulong sbi_hart_expected_trap_addr(void)
{
- return (ulong)sbi_hart_unpriv_trap;
+ return (ulong)sbi_hart_expected_trap;
}
void sbi_hart_delegation_dump(struct sbi_scratch *scratch);
libsbi-objs-y += sbi_tlb.o
libsbi-objs-y += sbi_trap.o
libsbi-objs-y += sbi_unpriv.o
-libsbi-objs-y += sbi_unpriv_trap.o
+libsbi-objs-y += sbi_expected_trap.o
#include <sbi/sbi_trap.h>
/*
- * We assume that faulting unpriv load/store instruction is
- * is 4-byte long and blindly increment SEPC by 4.
+ * We assume that faulting instruction is is 4-byte long and blindly
+ * increment SEPC by 4.
*
* The trap info will be saved as follows:
* A3 <- pointer struct sbi_trap_info
*/
.align 3
- .global __sbi_unpriv_trap
-__sbi_unpriv_trap:
+ .global __sbi_expected_trap
+__sbi_expected_trap:
/* Without H-extension so, MTVAL2 and MTINST CSRs not available */
csrr a4, CSR_MEPC
REG_S a4, SBI_TRAP_INFO_OFFSET(epc)(a3)
mret
.align 3
- .global __sbi_unpriv_trap_hext
-__sbi_unpriv_trap_hext:
+ .global __sbi_expected_trap_hext
+__sbi_expected_trap_hext:
/* With H-extension so, MTVAL2 and MTINST CSRs available */
csrr a4, CSR_MEPC
REG_S a4, SBI_TRAP_INFO_OFFSET(epc)(a3)
#include <sbi/sbi_hart.h>
#include <sbi/sbi_platform.h>
-extern void __sbi_unpriv_trap(void);
-extern void __sbi_unpriv_trap_hext(void);
+extern void __sbi_expected_trap(void);
+extern void __sbi_expected_trap_hext(void);
-void (*sbi_hart_unpriv_trap)(void) = &__sbi_unpriv_trap;
+void (*sbi_hart_expected_trap)(void) = &__sbi_expected_trap;
static void mstatus_init(struct sbi_scratch *scratch, u32 hartid)
{
if (cold_boot) {
if (misa_extension('H'))
- sbi_hart_unpriv_trap = &__sbi_unpriv_trap_hext;
+ sbi_hart_expected_trap = &__sbi_expected_trap_hext;
}
mstatus_init(scratch, hartid);
register ulong tinfo asm("a3"); \
register ulong ttmp asm("a4"); \
register ulong mstatus asm("a5"); \
- register ulong mtvec asm("a6") = sbi_hart_unpriv_trap_addr(); \
+ register ulong mtvec asm("a6") = sbi_hart_expected_trap_addr(); \
type ret = 0; \
trap->cause = 0; \
asm volatile( \
register ulong tinfo asm("a3"); \
register ulong ttmp asm("a4"); \
register ulong mstatus asm("a5"); \
- register ulong mtvec asm("a6") = sbi_hart_unpriv_trap_addr(); \
+ register ulong mtvec asm("a6") = sbi_hart_expected_trap_addr(); \
trap->cause = 0; \
asm volatile( \
"add %[tinfo], %[taddr], zero\n" \
register ulong tinfo asm("a3");
register ulong ttmp asm("a4");
register ulong mstatus asm("a5");
- register ulong mtvec asm("a6") = sbi_hart_unpriv_trap_addr();
+ register ulong mtvec asm("a6") = sbi_hart_expected_trap_addr();
ulong insn = 0;
trap->cause = 0;