2005-06-29 Richard Henderson <rth@redhat.com>
+ * config/alpha/alpha.md (vec_shl_<VEC>, vec_shr_<VEC>): New.
+
+2005-06-29 Richard Henderson <rth@redhat.com>
+
* tree-vect-transform.c (vect_min_worthwhile_factor): Declare.
(vect_create_epilog_for_reduction): Don't use vec_shr if the
operation is emulated.
""
"eqv %1,%2,%0"
[(set_attr "type" "ilog")])
+
+(define_expand "vec_shl_<mode>"
+ [(set (match_operand:VEC 0 "register_operand" "")
+ (ashift:DI (match_operand:VEC 1 "register_operand" "")
+ (match_operand:DI 2 "reg_or_6bit_operand" "")))]
+ ""
+{
+ operands[0] = gen_lowpart (DImode, operands[0]);
+ operands[1] = gen_lowpart (DImode, operands[1]);
+})
+
+(define_expand "vec_shr_<mode>"
+ [(set (match_operand:VEC 0 "register_operand" "")
+ (lshiftrt:DI (match_operand:VEC 1 "register_operand" "")
+ (match_operand:DI 2 "reg_or_6bit_operand" "")))]
+ ""
+{
+ operands[0] = gen_lowpart (DImode, operands[0]);
+ operands[1] = gen_lowpart (DImode, operands[1]);
+})
\f
;; Bit field extract patterns which use ext[wlq][lh]