&gpio {
/* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
- pex-perst-n {
+ pex-perst-n-hog {
gpio-hog;
gpios = <TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
output-high;
&gpio {
/* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
- pex-perst-n {
+ pex-perst-n-hog {
gpio-hog;
gpios = <TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
output-high;
&gpio {
/* I210 Gigabit Ethernet Controller Reset */
- lan-reset-n {
+ lan-reset-n-hog {
gpio-hog;
gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
output-high;
};
/* Control MXM3 pin 26 Reset Module Output Carrier Input */
- reset-moci-ctrl {
+ reset-moci-ctrl-hog {
gpio-hog;
gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
output-high;
&gpio {
/* I210 Gigabit Ethernet Controller Reset */
- lan-reset-n {
+ lan-reset-n-hog {
gpio-hog;
gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
output-high;
};
/* Control MXM3 pin 26 Reset Module Output Carrier Input */
- reset-moci-ctrl {
+ reset-moci-ctrl-hog {
gpio-hog;
gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
output-high;
};
&gpio {
- lan-reset-n {
+ lan-reset-n-hog {
gpio-hog;
gpios = <TEGRA_GPIO(V, 4) GPIO_ACTIVE_HIGH>;
output-high;
};
/* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */
- npwe {
+ npwe-hog {
gpio-hog;
gpios = <TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
output-high;
};
/* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */
- rdnwr {
+ rdnwr-hog {
gpio-hog;
gpios = <TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>;
output-low;
&gpio {
/* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
- pex-perst-n {
+ pex-perst-n-hog {
gpio-hog;
gpios = <TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
output-high;
&gpio {
/* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */
- pex-perst-n {
+ pex-perst-n-hog {
gpio-hog;
gpios = <TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
output-high;
};
&gpio {
- lan-reset-n {
+ lan-reset-n-hog {
gpio-hog;
gpios = <TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>;
output-high;