(ACPI_BITMASK_RT_CLOCK_ENABLE |
ACPI_BITMASK_POWER_BUTTON_ENABLE |
ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
- ACPI_BITMASK_TIMER_ENABLE)) != 0);
+ ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
+ (((s->gpe.sts & s->gpe.en) & PIIX4_PCI_HOTPLUG_STATUS) != 0);
+
qemu_set_irq(s->irq, sci_level);
/* schedule a timer interruption if needed */
if ((s->pmen & ACPI_BITMASK_TIMER_ENABLE) &&
static uint32_t gpe_readb(void *opaque, uint32_t addr)
{
uint32_t val = 0;
- struct gpe_regs *g = opaque;
+ PIIX4PMState *s = opaque;
+ struct gpe_regs *g = &s->gpe;
+
switch (addr) {
case GPE_BASE:
case GPE_BASE + 1:
static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
{
- struct gpe_regs *g = opaque;
+ PIIX4PMState *s = opaque;
+ struct gpe_regs *g = &s->gpe;
+
switch (addr) {
case GPE_BASE:
case GPE_BASE + 1:
break;
default:
break;
- }
+ }
+
+ pm_update_sci(s);
PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
}
static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
{
- struct gpe_regs *gpe = &s->gpe;
struct pci_status *pci0_status = &s->pci0_status;
- register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, gpe);
- register_ioport_read(GPE_BASE, 4, 1, gpe_readb, gpe);
+ register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, s);
+ register_ioport_read(GPE_BASE, 4, 1, gpe_readb, s);
register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, pci0_status);
} else {
disable_device(s, slot);
}
- if (s->gpe.en & 2) {
- qemu_set_irq(s->irq, 1);
- qemu_set_irq(s->irq, 0);
- }
+
+ pm_update_sci(s);
+
return 0;
}