clk: update pcie pll config

PD#148744: update axg pcie pll config

Change-Id: I4adf79f40f70cd23427f018e7030aeaa9bd080c4
Signed-off-by: Yun Cai <yun.cai@amlogic.com>

diff --git a/drivers/amlogic/clk/axg/axg.h b/drivers/amlogic/clk/axg/axg.h
index d36ffd8..d00dd05 100644 (file)
--- a/drivers/amlogic/clk/axg/axg.h
+++ b/drivers/amlogic/clk/axg/axg.h
@@ -274,7 +274,7 @@ static const struct pll_rate_table axg_gp0_pll_rate_table[] = {
 };
 
 static const struct pll_rate_table axg_pcie_pll_rate_table[] = {
-       PLL_FRAC_RATE(100000000, 66, 1, 1, 3, 683),
+       PLL_FRAC_RATE(100000000, 200, 3, 1, 3, 0),
        { /* sentinel */ },
 };
 #endif /* __AXG_H */

diff --git a/drivers/amlogic/pci/pcie-amlogic.c b/drivers/amlogic/pci/pcie-amlogic.c
index e9907d4..c8d6fbd 100644 (file)
--- a/drivers/amlogic/pci/pcie-amlogic.c
+++ b/drivers/amlogic/pci/pcie-amlogic.c
@@ -725,7 +725,7 @@ static int __init amlogic_pcie_probe(struct platform_device *pdev)
                        goto fail_pcie;
                }
 
-               if (clk_get_rate(amlogic_pcie->bus_clk) == rate) {
+               if (clk_get_rate(amlogic_pcie->bus_clk) != rate) {
                        ret = -ENODEV;
                        goto fail_pcie;
                }