igc: Set QBVCYCLET_S to 0 for TSN Basic Scheduling
authorMuhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com>
Fri, 9 Jul 2021 23:40:17 +0000 (07:40 +0800)
committerTony Nguyen <anthony.l.nguyen@intel.com>
Tue, 20 Jul 2021 23:11:36 +0000 (16:11 -0700)
According to datasheet section 8.12.19, when there's no TSN offloading
Shadow_QbvCycle bit[29:0] must be set to zero for basic scheduling.

Signed-off-by: Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com>
Tested-by: Dvora Fuxbrumer <dvorax.fuxbrumer@linux.intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
drivers/net/ethernet/intel/igc/igc_tsn.c

index 174103c..4dbbb8a 100644 (file)
@@ -52,7 +52,7 @@ static int igc_tsn_disable_offload(struct igc_adapter *adapter)
                wr32(IGC_ENDQT(i), NSEC_PER_SEC);
        }
 
-       wr32(IGC_QBVCYCLET_S, NSEC_PER_SEC);
+       wr32(IGC_QBVCYCLET_S, 0);
        wr32(IGC_QBVCYCLET, NSEC_PER_SEC);
 
        adapter->flags &= ~IGC_FLAG_TSN_QBV_ENABLED;