iommu/arm-smmu: Add reset implementation hook

Reset is an activity rife with implementation-defined poking. Add a
corresponding hook, and use it to encapsulate the existing MMU-500
details.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>

diff --git a/drivers/iommu/arm-smmu-impl.c b/drivers/iommu/arm-smmu-impl.c
index 6964179..4dc8b1c 100644 (file)
--- a/drivers/iommu/arm-smmu-impl.c
+++ b/drivers/iommu/arm-smmu-impl.c
@@ -4,6 +4,7 @@
 
 #define pr_fmt(fmt) "arm-smmu: " fmt
 
+#include <linux/bitfield.h>
 #include <linux/of.h>
 
 #include "arm-smmu.h"
@@ -67,6 +68,51 @@ const struct arm_smmu_impl cavium_impl = {
 };
 
 
+#define ARM_MMU500_ACTLR_CPRE          (1 << 1)
+
+#define ARM_MMU500_ACR_CACHE_LOCK      (1 << 26)
+#define ARM_MMU500_ACR_S2CRB_TLBEN     (1 << 10)
+#define ARM_MMU500_ACR_SMTNMB_TLBEN    (1 << 8)
+
+static int arm_mmu500_reset(struct arm_smmu_device *smmu)
+{
+       u32 reg, major;
+       int i;
+       /*
+        * On MMU-500 r2p0 onwards we need to clear ACR.CACHE_LOCK before
+        * writes to the context bank ACTLRs will stick. And we just hope that
+        * Secure has also cleared SACR.CACHE_LOCK for this to take effect...
+        */
+       reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID7);
+       major = FIELD_GET(ID7_MAJOR, reg);
+       reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sACR);
+       if (major >= 2)
+               reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
+       /*
+        * Allow unmatched Stream IDs to allocate bypass
+        * TLB entries for reduced latency.
+        */
+       reg |= ARM_MMU500_ACR_SMTNMB_TLBEN | ARM_MMU500_ACR_S2CRB_TLBEN;
+       arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sACR, reg);
+
+       /*
+        * Disable MMU-500's not-particularly-beneficial next-page
+        * prefetcher for the sake of errata #841119 and #826419.
+        */
+       for (i = 0; i < smmu->num_context_banks; ++i) {
+               reg = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR);
+               reg &= ~ARM_MMU500_ACTLR_CPRE;
+               arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, reg);
+       }
+
+       return 0;
+}
+
+const struct arm_smmu_impl arm_mmu500_impl = {
+       .reset = arm_mmu500_reset,
+};
+
+
 struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu)
 {
        /*
@@ -76,6 +122,9 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu)
         * mutually-exclusive assignments.
         */
        switch (smmu->model) {
+       case ARM_MMU500:
+               smmu->impl = &arm_mmu500_impl;
+               break;
        case CAVIUM_SMMUV2:
                smmu->impl = &cavium_impl;
                break;

diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 362b6b5..fc98992 100644 (file)
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -54,12 +54,6 @@
  */
 #define QCOM_DUMMY_VAL -1
 
-#define ARM_MMU500_ACTLR_CPRE          (1 << 1)
-
-#define ARM_MMU500_ACR_CACHE_LOCK      (1 << 26)
-#define ARM_MMU500_ACR_S2CRB_TLBEN     (1 << 10)
-#define ARM_MMU500_ACR_SMTNMB_TLBEN    (1 << 8)
-
 #define TLB_LOOP_TIMEOUT               1000000 /* 1s! */
 #define TLB_SPIN_COUNT                 10
 
@@ -1574,7 +1568,7 @@ static struct iommu_ops arm_smmu_ops = {
 static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
 {
        int i;
-       u32 reg, major;
+       u32 reg;
 
        /* clear global FSR */
        reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSR);
@@ -1587,38 +1581,10 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
        for (i = 0; i < smmu->num_mapping_groups; ++i)
                arm_smmu_write_sme(smmu, i);
 
-       if (smmu->model == ARM_MMU500) {
-               /*
-                * Before clearing ARM_MMU500_ACTLR_CPRE, need to
-                * clear CACHE_LOCK bit of ACR first. And, CACHE_LOCK
-                * bit is only present in MMU-500r2 onwards.
-                */
-               reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID7);
-               major = FIELD_GET(ID7_MAJOR, reg);
-               reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sACR);
-               if (major >= 2)
-                       reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
-               /*
-                * Allow unmatched Stream IDs to allocate bypass
-                * TLB entries for reduced latency.
-                */
-               reg |= ARM_MMU500_ACR_SMTNMB_TLBEN | ARM_MMU500_ACR_S2CRB_TLBEN;
-               arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sACR, reg);
-       }
-
        /* Make sure all context banks are disabled and clear CB_FSR  */
        for (i = 0; i < smmu->num_context_banks; ++i) {
                arm_smmu_write_context_bank(smmu, i);
                arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, FSR_FAULT);
-               /*
-                * Disable MMU-500's not-particularly-beneficial next-page
-                * prefetcher for the sake of errata #841119 and #826419.
-                */
-               if (smmu->model == ARM_MMU500) {
-                       reg = arm_smmu_cb_read(smmu, i, ARM_SMMU_CB_ACTLR);
-                       reg &= ~ARM_MMU500_ACTLR_CPRE;
-                       arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, reg);
-               }
        }
 
        /* Invalidate the TLB, just in case */
@@ -1652,6 +1618,9 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
        if (smmu->features & ARM_SMMU_FEAT_EXIDS)
                reg |= sCR0_EXIDENABLE;
 
+       if (smmu->impl && smmu->impl->reset)
+               smmu->impl->reset(smmu);
+
        /* Push the button */
        arm_smmu_tlb_sync_global(smmu);
        arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sCR0, reg);

diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h
index f4e90f3..ddafe87 100644 (file)
--- a/drivers/iommu/arm-smmu.h
+++ b/drivers/iommu/arm-smmu.h
@@ -288,6 +288,7 @@ struct arm_smmu_impl {
        void (*write_reg64)(struct arm_smmu_device *smmu, int page, int offset,
                            u64 val);
        int (*cfg_probe)(struct arm_smmu_device *smmu);
+       int (*reset)(struct arm_smmu_device *smmu);
 };
 
 static inline void __iomem *arm_smmu_page(struct arm_smmu_device *smmu, int n)