usb: dwc3: core: do not use 3.0 clock when operating in 2.0 mode

In the 3.0 device core, if the core is programmed to operate in
2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes
the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe)
clock. Enabling this feature allows the pipe3 clock to be not-running
when forcibly operating in 2.0 device mode.

Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Link: https://lore.kernel.org/r/20220228135700.1089526-6-pgwipeout@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 18adddfba3da81cd6c8b3c8ddc6d1cd9e584ae0c..416d83a055fe9e277e418b238045f552c4b3a7da 100644 (file)
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1167,6 +1167,11 @@ static int dwc3_core_init(struct dwc3 *dwc)
                if (dwc->parkmode_disable_ss_quirk)
                        reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
 
+               if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
+                   (dwc->maximum_speed == USB_SPEED_HIGH ||
+                    dwc->maximum_speed == USB_SPEED_FULL))
+                       reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
+
                dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
        }
 

diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index eb9c1efced05bcdab31f304337fd42029d86f703..ea3ca04406bbd617c2172c940190752113834491 100644 (file)
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -259,6 +259,7 @@
 /* Global User Control 1 Register */
 #define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT      BIT(31)
 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS     BIT(28)
+#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK        BIT(26)
 #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW          BIT(24)
 #define DWC3_GUCTL1_PARKMODE_DISABLE_SS                BIT(17)