; CHECK: andv b[[REDUCE:[0-9]+]], [[PG]], z0.b
; CHECK: fmov w0, s[[REDUCE]]
; CHECK: ret
- %res = call i8 @llvm.experimental.vector.reduce.and.v8i8(<8 x i8> %a)
+ %res = call i8 @llvm.vector.reduce.and.v8i8(<8 x i8> %a)
ret i8 %res
}
; CHECK: andv b[[REDUCE:[0-9]+]], [[PG]], z0.b
; CHECK: fmov w0, s[[REDUCE]]
; CHECK: ret
- %res = call i8 @llvm.experimental.vector.reduce.and.v16i8(<16 x i8> %a)
+ %res = call i8 @llvm.vector.reduce.and.v16i8(<16 x i8> %a)
ret i8 %res
}
; CHECK-NEXT: fmov w0, s[[REDUCE]]
; CHECK-NEXT: ret
%op = load <32 x i8>, <32 x i8>* %a
- %res = call i8 @llvm.experimental.vector.reduce.and.v32i8(<32 x i8> %op)
+ %res = call i8 @llvm.vector.reduce.and.v32i8(<32 x i8> %op)
ret i8 %res
}
; VBITS_EQ_256-NEXT: ret
%op = load <64 x i8>, <64 x i8>* %a
- %res = call i8 @llvm.experimental.vector.reduce.and.v64i8(<64 x i8> %op)
+ %res = call i8 @llvm.vector.reduce.and.v64i8(<64 x i8> %op)
ret i8 %res
}
; VBITS_GE_1024-NEXT: fmov w0, s[[REDUCE]]
; VBITS_GE_1024-NEXT: ret
%op = load <128 x i8>, <128 x i8>* %a
- %res = call i8 @llvm.experimental.vector.reduce.and.v128i8(<128 x i8> %op)
+ %res = call i8 @llvm.vector.reduce.and.v128i8(<128 x i8> %op)
ret i8 %res
}
; VBITS_GE_2048-NEXT: fmov w0, s[[REDUCE]]
; VBITS_GE_2048-NEXT: ret
%op = load <256 x i8>, <256 x i8>* %a
- %res = call i8 @llvm.experimental.vector.reduce.and.v256i8(<256 x i8> %op)
+ %res = call i8 @llvm.vector.reduce.and.v256i8(<256 x i8> %op)
ret i8 %res
}
; CHECK: andv h[[REDUCE:[0-9]+]], [[PG]], z0.h
; CHECK: fmov w0, s[[REDUCE]]
; CHECK: ret
- %res = call i16 @llvm.experimental.vector.reduce.and.v4i16(<4 x i16> %a)
+ %res = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> %a)
ret i16 %res
}
; CHECK: andv h[[REDUCE:[0-9]+]], [[PG]], z0.h
; CHECK: fmov w0, s[[REDUCE]]
; CHECK: ret
- %res = call i16 @llvm.experimental.vector.reduce.and.v8i16(<8 x i16> %a)
+ %res = call i16 @llvm.vector.reduce.and.v8i16(<8 x i16> %a)
ret i16 %res
}
; CHECK-NEXT: fmov w0, s[[REDUCE]]
; CHECK-NEXT: ret
%op = load <16 x i16>, <16 x i16>* %a
- %res = call i16 @llvm.experimental.vector.reduce.and.v16i16(<16 x i16> %op)
+ %res = call i16 @llvm.vector.reduce.and.v16i16(<16 x i16> %op)
ret i16 %res
}
; VBITS_EQ_256-NEXT: fmov w0, s[[REDUCE]]
; VBITS_EQ_256-NEXT: ret
%op = load <32 x i16>, <32 x i16>* %a
- %res = call i16 @llvm.experimental.vector.reduce.and.v32i16(<32 x i16> %op)
+ %res = call i16 @llvm.vector.reduce.and.v32i16(<32 x i16> %op)
ret i16 %res
}
; VBITS_GE_1024-NEXT: fmov w0, s[[REDUCE]]
; VBITS_GE_1024-NEXT: ret
%op = load <64 x i16>, <64 x i16>* %a
- %res = call i16 @llvm.experimental.vector.reduce.and.v64i16(<64 x i16> %op)
+ %res = call i16 @llvm.vector.reduce.and.v64i16(<64 x i16> %op)
ret i16 %res
}
; VBITS_GE_2048-NEXT: fmov w0, s[[REDUCE]]
; VBITS_GE_2048-NEXT: ret
%op = load <128 x i16>, <128 x i16>* %a
- %res = call i16 @llvm.experimental.vector.reduce.and.v128i16(<128 x i16> %op)
+ %res = call i16 @llvm.vector.reduce.and.v128i16(<128 x i16> %op)
ret i16 %res
}
; CHECK: andv [[REDUCE:s[0-9]+]], [[PG]], z0.s
; CHECK: fmov w0, [[REDUCE]]
; CHECK: ret
- %res = call i32 @llvm.experimental.vector.reduce.and.v2i32(<2 x i32> %a)
+ %res = call i32 @llvm.vector.reduce.and.v2i32(<2 x i32> %a)
ret i32 %res
}
; CHECK: andv [[REDUCE:s[0-9]+]], [[PG]], z0.s
; CHECK: fmov w0, [[REDUCE]]
; CHECK: ret
- %res = call i32 @llvm.experimental.vector.reduce.and.v4i32(<4 x i32> %a)
+ %res = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> %a)
ret i32 %res
}
; CHECK-NEXT: fmov w0, [[REDUCE]]
; CHECK-NEXT: ret
%op = load <8 x i32>, <8 x i32>* %a
- %res = call i32 @llvm.experimental.vector.reduce.and.v8i32(<8 x i32> %op)
+ %res = call i32 @llvm.vector.reduce.and.v8i32(<8 x i32> %op)
ret i32 %res
}
; VBITS_EQ_256-NEXT: fmov w0, [[REDUCE]]
; VBITS_EQ_256-NEXT: ret
%op = load <16 x i32>, <16 x i32>* %a
- %res = call i32 @llvm.experimental.vector.reduce.and.v16i32(<16 x i32> %op)
+ %res = call i32 @llvm.vector.reduce.and.v16i32(<16 x i32> %op)
ret i32 %res
}
; VBITS_GE_1024-NEXT: fmov w0, [[REDUCE]]
; VBITS_GE_1024-NEXT: ret
%op = load <32 x i32>, <32 x i32>* %a
- %res = call i32 @llvm.experimental.vector.reduce.and.v32i32(<32 x i32> %op)
+ %res = call i32 @llvm.vector.reduce.and.v32i32(<32 x i32> %op)
ret i32 %res
}
; VBITS_GE_2048-NEXT: fmov w0, [[REDUCE]]
; VBITS_GE_2048-NEXT: ret
%op = load <64 x i32>, <64 x i32>* %a
- %res = call i32 @llvm.experimental.vector.reduce.and.v64i32(<64 x i32> %op)
+ %res = call i32 @llvm.vector.reduce.and.v64i32(<64 x i32> %op)
ret i32 %res
}
; CHECK-LABEL: andv_v1i64:
; CHECK: fmov x0, d0
; CHECK: ret
- %res = call i64 @llvm.experimental.vector.reduce.and.v1i64(<1 x i64> %a)
+ %res = call i64 @llvm.vector.reduce.and.v1i64(<1 x i64> %a)
ret i64 %res
}
; CHECK: andv [[REDUCE:d[0-9]+]], [[PG]], z0.d
; CHECK: fmov x0, [[REDUCE]]
; CHECK: ret
- %res = call i64 @llvm.experimental.vector.reduce.and.v2i64(<2 x i64> %a)
+ %res = call i64 @llvm.vector.reduce.and.v2i64(<2 x i64> %a)
ret i64 %res
}
; CHECK-NEXT: fmov x0, [[REDUCE]]
; CHECK-NEXT: ret
%op = load <4 x i64>, <4 x i64>* %a
- %res = call i64 @llvm.experimental.vector.reduce.and.v4i64(<4 x i64> %op)
+ %res = call i64 @llvm.vector.reduce.and.v4i64(<4 x i64> %op)
ret i64 %res
}
; VBITS_EQ_256-NEXT: fmov x0, [[REDUCE]]
; VBITS_EQ_256-NEXT: ret
%op = load <8 x i64>, <8 x i64>* %a
- %res = call i64 @llvm.experimental.vector.reduce.and.v8i64(<8 x i64> %op)
+ %res = call i64 @llvm.vector.reduce.and.v8i64(<8 x i64> %op)
ret i64 %res
}
; VBITS_GE_1024-NEXT: fmov x0, [[REDUCE]]
; VBITS_GE_1024-NEXT: ret
%op = load <16 x i64>, <16 x i64>* %a
- %res = call i64 @llvm.experimental.vector.reduce.and.v16i64(<16 x i64> %op)
+ %res = call i64 @llvm.vector.reduce.and.v16i64(<16 x i64> %op)
ret i64 %res
}
; VBITS_GE_2048-NEXT: fmov x0, [[REDUCE]]
; VBITS_GE_2048-NEXT: ret
%op = load <32 x i64>, <32 x i64>* %a
- %res = call i64 @llvm.experimental.vector.reduce.and.v32i64(<32 x i64> %op)
+ %res = call i64 @llvm.vector.reduce.and.v32i64(<32 x i64> %op)
ret i64 %res
}
; CHECK: eorv b[[REDUCE:[0-9]+]], [[PG]], z0.b
; CHECK: fmov w0, s[[REDUCE]]
; CHECK: ret
- %res = call i8 @llvm.experimental.vector.reduce.xor.v8i8(<8 x i8> %a)
+ %res = call i8 @llvm.vector.reduce.xor.v8i8(<8 x i8> %a)
ret i8 %res
}
; CHECK: eorv b[[REDUCE:[0-9]+]], [[PG]], z0.b
; CHECK: fmov w0, s[[REDUCE]]
; CHECK: ret
- %res = call i8 @llvm.experimental.vector.reduce.xor.v16i8(<16 x i8> %a)
+ %res = call i8 @llvm.vector.reduce.xor.v16i8(<16 x i8> %a)
ret i8 %res
}
; CHECK-NEXT: fmov w0, s[[REDUCE]]
; CHECK-NEXT: ret
%op = load <32 x i8>, <32 x i8>* %a
- %res = call i8 @llvm.experimental.vector.reduce.xor.v32i8(<32 x i8> %op)
+ %res = call i8 @llvm.vector.reduce.xor.v32i8(<32 x i8> %op)
ret i8 %res
}
; VBITS_EQ_256-NEXT: ret
%op = load <64 x i8>, <64 x i8>* %a
- %res = call i8 @llvm.experimental.vector.reduce.xor.v64i8(<64 x i8> %op)
+ %res = call i8 @llvm.vector.reduce.xor.v64i8(<64 x i8> %op)
ret i8 %res
}
; VBITS_GE_1024-NEXT: fmov w0, s[[REDUCE]]
; VBITS_GE_1024-NEXT: ret
%op = load <128 x i8>, <128 x i8>* %a
- %res = call i8 @llvm.experimental.vector.reduce.xor.v128i8(<128 x i8> %op)
+ %res = call i8 @llvm.vector.reduce.xor.v128i8(<128 x i8> %op)
ret i8 %res
}
; VBITS_GE_2048-NEXT: fmov w0, s[[REDUCE]]
; VBITS_GE_2048-NEXT: ret
%op = load <256 x i8>, <256 x i8>* %a
- %res = call i8 @llvm.experimental.vector.reduce.xor.v256i8(<256 x i8> %op)
+ %res = call i8 @llvm.vector.reduce.xor.v256i8(<256 x i8> %op)
ret i8 %res
}
; CHECK: eorv h[[REDUCE:[0-9]+]], [[PG]], z0.h
; CHECK: fmov w0, s[[REDUCE]]
; CHECK: ret
- %res = call i16 @llvm.experimental.vector.reduce.xor.v4i16(<4 x i16> %a)
+ %res = call i16 @llvm.vector.reduce.xor.v4i16(<4 x i16> %a)
ret i16 %res
}
; CHECK: eorv h[[REDUCE:[0-9]+]], [[PG]], z0.h
; CHECK: fmov w0, s[[REDUCE]]
; CHECK: ret
- %res = call i16 @llvm.experimental.vector.reduce.xor.v8i16(<8 x i16> %a)
+ %res = call i16 @llvm.vector.reduce.xor.v8i16(<8 x i16> %a)
ret i16 %res
}
; CHECK-NEXT: fmov w0, s[[REDUCE]]
; CHECK-NEXT: ret
%op = load <16 x i16>, <16 x i16>* %a
- %res = call i16 @llvm.experimental.vector.reduce.xor.v16i16(<16 x i16> %op)
+ %res = call i16 @llvm.vector.reduce.xor.v16i16(<16 x i16> %op)
ret i16 %res
}
; VBITS_EQ_256-NEXT: fmov w0, s[[REDUCE]]
; VBITS_EQ_256-NEXT: ret
%op = load <32 x i16>, <32 x i16>* %a
- %res = call i16 @llvm.experimental.vector.reduce.xor.v32i16(<32 x i16> %op)
+ %res = call i16 @llvm.vector.reduce.xor.v32i16(<32 x i16> %op)
ret i16 %res
}
; VBITS_GE_1024-NEXT: fmov w0, s[[REDUCE]]
; VBITS_GE_1024-NEXT: ret
%op = load <64 x i16>, <64 x i16>* %a
- %res = call i16 @llvm.experimental.vector.reduce.xor.v64i16(<64 x i16> %op)
+ %res = call i16 @llvm.vector.reduce.xor.v64i16(<64 x i16> %op)
ret i16 %res
}
; VBITS_GE_2048-NEXT: fmov w0, s[[REDUCE]]
; VBITS_GE_2048-NEXT: ret
%op = load <128 x i16>, <128 x i16>* %a
- %res = call i16 @llvm.experimental.vector.reduce.xor.v128i16(<128 x i16> %op)
+ %res = call i16 @llvm.vector.reduce.xor.v128i16(<128 x i16> %op)
ret i16 %res
}
; CHECK: eorv [[REDUCE:s[0-9]+]], [[PG]], z0.s
; CHECK: fmov w0, [[REDUCE]]
; CHECK: ret
- %res = call i32 @llvm.experimental.vector.reduce.xor.v2i32(<2 x i32> %a)
+ %res = call i32 @llvm.vector.reduce.xor.v2i32(<2 x i32> %a)
ret i32 %res
}
; CHECK: eorv [[REDUCE:s[0-9]+]], [[PG]], z0.s
; CHECK: fmov w0, [[REDUCE]]
; CHECK: ret
- %res = call i32 @llvm.experimental.vector.reduce.xor.v4i32(<4 x i32> %a)
+ %res = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> %a)
ret i32 %res
}
; CHECK-NEXT: fmov w0, [[REDUCE]]
; CHECK-NEXT: ret
%op = load <8 x i32>, <8 x i32>* %a
- %res = call i32 @llvm.experimental.vector.reduce.xor.v8i32(<8 x i32> %op)
+ %res = call i32 @llvm.vector.reduce.xor.v8i32(<8 x i32> %op)
ret i32 %res
}
; VBITS_EQ_256-NEXT: fmov w0, [[REDUCE]]
; VBITS_EQ_256-NEXT: ret
%op = load <16 x i32>, <16 x i32>* %a
- %res = call i32 @llvm.experimental.vector.reduce.xor.v16i32(<16 x i32> %op)
+ %res = call i32 @llvm.vector.reduce.xor.v16i32(<16 x i32> %op)
ret i32 %res
}
; VBITS_GE_1024-NEXT: fmov w0, [[REDUCE]]
; VBITS_GE_1024-NEXT: ret
%op = load <32 x i32>, <32 x i32>* %a
- %res = call i32 @llvm.experimental.vector.reduce.xor.v32i32(<32 x i32> %op)
+ %res = call i32 @llvm.vector.reduce.xor.v32i32(<32 x i32> %op)
ret i32 %res
}
; VBITS_GE_2048-NEXT: fmov w0, [[REDUCE]]
; VBITS_GE_2048-NEXT: ret
%op = load <64 x i32>, <64 x i32>* %a
- %res = call i32 @llvm.experimental.vector.reduce.xor.v64i32(<64 x i32> %op)
+ %res = call i32 @llvm.vector.reduce.xor.v64i32(<64 x i32> %op)
ret i32 %res
}
; CHECK-LABEL: eorv_v1i64:
; CHECK: fmov x0, d0
; CHECK: ret
- %res = call i64 @llvm.experimental.vector.reduce.xor.v1i64(<1 x i64> %a)
+ %res = call i64 @llvm.vector.reduce.xor.v1i64(<1 x i64> %a)
ret i64 %res
}
; CHECK: eorv [[REDUCE:d[0-9]+]], [[PG]], z0.d
; CHECK: fmov x0, [[REDUCE]]
; CHECK: ret
- %res = call i64 @llvm.experimental.vector.reduce.xor.v2i64(<2 x i64> %a)
+ %res = call i64 @llvm.vector.reduce.xor.v2i64(<2 x i64> %a)
ret i64 %res
}
; CHECK-NEXT: fmov x0, [[REDUCE]]
; CHECK-NEXT: ret
%op = load <4 x i64>, <4 x i64>* %a
- %res = call i64 @llvm.experimental.vector.reduce.xor.v4i64(<4 x i64> %op)
+ %res = call i64 @llvm.vector.reduce.xor.v4i64(<4 x i64> %op)
ret i64 %res
}
; VBITS_EQ_256-NEXT: fmov x0, [[REDUCE]]
; VBITS_EQ_256-NEXT: ret
%op = load <8 x i64>, <8 x i64>* %a
- %res = call i64 @llvm.experimental.vector.reduce.xor.v8i64(<8 x i64> %op)
+ %res = call i64 @llvm.vector.reduce.xor.v8i64(<8 x i64> %op)
ret i64 %res
}
; VBITS_GE_1024-NEXT: fmov x0, [[REDUCE]]
; VBITS_GE_1024-NEXT: ret
%op = load <16 x i64>, <16 x i64>* %a
- %res = call i64 @llvm.experimental.vector.reduce.xor.v16i64(<16 x i64> %op)
+ %res = call i64 @llvm.vector.reduce.xor.v16i64(<16 x i64> %op)
ret i64 %res
}
; VBITS_GE_2048-NEXT: fmov x0, [[REDUCE]]
; VBITS_GE_2048-NEXT: ret
%op = load <32 x i64>, <32 x i64>* %a
- %res = call i64 @llvm.experimental.vector.reduce.xor.v32i64(<32 x i64> %op)
+ %res = call i64 @llvm.vector.reduce.xor.v32i64(<32 x i64> %op)
ret i64 %res
}
; CHECK: orv b[[REDUCE:[0-9]+]], [[PG]], z0.b
; CHECK: fmov w0, s[[REDUCE]]
; CHECK: ret
- %res = call i8 @llvm.experimental.vector.reduce.or.v8i8(<8 x i8> %a)
+ %res = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> %a)
ret i8 %res
}
; CHECK: orv b[[REDUCE:[0-9]+]], [[PG]], z0.b
; CHECK: fmov w0, s[[REDUCE]]
; CHECK: ret
- %res = call i8 @llvm.experimental.vector.reduce.or.v16i8(<16 x i8> %a)
+ %res = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> %a)
ret i8 %res
}
; CHECK-NEXT: fmov w0, s[[REDUCE]]
; CHECK-NEXT: ret
%op = load <32 x i8>, <32 x i8>* %a
- %res = call i8 @llvm.experimental.vector.reduce.or.v32i8(<32 x i8> %op)
+ %res = call i8 @llvm.vector.reduce.or.v32i8(<32 x i8> %op)
ret i8 %res
}
; VBITS_EQ_256-NEXT: ret
%op = load <64 x i8>, <64 x i8>* %a
- %res = call i8 @llvm.experimental.vector.reduce.or.v64i8(<64 x i8> %op)
+ %res = call i8 @llvm.vector.reduce.or.v64i8(<64 x i8> %op)
ret i8 %res
}
; VBITS_GE_1024-NEXT: fmov w0, s[[REDUCE]]
; VBITS_GE_1024-NEXT: ret
%op = load <128 x i8>, <128 x i8>* %a
- %res = call i8 @llvm.experimental.vector.reduce.or.v128i8(<128 x i8> %op)
+ %res = call i8 @llvm.vector.reduce.or.v128i8(<128 x i8> %op)
ret i8 %res
}
; VBITS_GE_2048-NEXT: fmov w0, s[[REDUCE]]
; VBITS_GE_2048-NEXT: ret
%op = load <256 x i8>, <256 x i8>* %a
- %res = call i8 @llvm.experimental.vector.reduce.or.v256i8(<256 x i8> %op)
+ %res = call i8 @llvm.vector.reduce.or.v256i8(<256 x i8> %op)
ret i8 %res
}
; CHECK: orv h[[REDUCE:[0-9]+]], [[PG]], z0.h
; CHECK: fmov w0, s[[REDUCE]]
; CHECK: ret
- %res = call i16 @llvm.experimental.vector.reduce.or.v4i16(<4 x i16> %a)
+ %res = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> %a)
ret i16 %res
}
; CHECK: orv h[[REDUCE:[0-9]+]], [[PG]], z0.h
; CHECK: fmov w0, s[[REDUCE]]
; CHECK: ret
- %res = call i16 @llvm.experimental.vector.reduce.or.v8i16(<8 x i16> %a)
+ %res = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> %a)
ret i16 %res
}
; CHECK-NEXT: fmov w0, s[[REDUCE]]
; CHECK-NEXT: ret
%op = load <16 x i16>, <16 x i16>* %a
- %res = call i16 @llvm.experimental.vector.reduce.or.v16i16(<16 x i16> %op)
+ %res = call i16 @llvm.vector.reduce.or.v16i16(<16 x i16> %op)
ret i16 %res
}
; VBITS_EQ_256-NEXT: fmov w0, s[[REDUCE]]
; VBITS_EQ_256-NEXT: ret
%op = load <32 x i16>, <32 x i16>* %a
- %res = call i16 @llvm.experimental.vector.reduce.or.v32i16(<32 x i16> %op)
+ %res = call i16 @llvm.vector.reduce.or.v32i16(<32 x i16> %op)
ret i16 %res
}
; VBITS_GE_1024-NEXT: fmov w0, s[[REDUCE]]
; VBITS_GE_1024-NEXT: ret
%op = load <64 x i16>, <64 x i16>* %a
- %res = call i16 @llvm.experimental.vector.reduce.or.v64i16(<64 x i16> %op)
+ %res = call i16 @llvm.vector.reduce.or.v64i16(<64 x i16> %op)
ret i16 %res
}
; VBITS_GE_2048-NEXT: fmov w0, s[[REDUCE]]
; VBITS_GE_2048-NEXT: ret
%op = load <128 x i16>, <128 x i16>* %a
- %res = call i16 @llvm.experimental.vector.reduce.or.v128i16(<128 x i16> %op)
+ %res = call i16 @llvm.vector.reduce.or.v128i16(<128 x i16> %op)
ret i16 %res
}
; CHECK: orv [[REDUCE:s[0-9]+]], [[PG]], z0.s
; CHECK: fmov w0, [[REDUCE]]
; CHECK: ret
- %res = call i32 @llvm.experimental.vector.reduce.or.v2i32(<2 x i32> %a)
+ %res = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> %a)
ret i32 %res
}
; CHECK: orv [[REDUCE:s[0-9]+]], [[PG]], z0.s
; CHECK: fmov w0, [[REDUCE]]
; CHECK: ret
- %res = call i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32> %a)
+ %res = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> %a)
ret i32 %res
}
; CHECK-NEXT: fmov w0, [[REDUCE]]
; CHECK-NEXT: ret
%op = load <8 x i32>, <8 x i32>* %a
- %res = call i32 @llvm.experimental.vector.reduce.or.v8i32(<8 x i32> %op)
+ %res = call i32 @llvm.vector.reduce.or.v8i32(<8 x i32> %op)
ret i32 %res
}
; VBITS_EQ_256-NEXT: fmov w0, [[REDUCE]]
; VBITS_EQ_256-NEXT: ret
%op = load <16 x i32>, <16 x i32>* %a
- %res = call i32 @llvm.experimental.vector.reduce.or.v16i32(<16 x i32> %op)
+ %res = call i32 @llvm.vector.reduce.or.v16i32(<16 x i32> %op)
ret i32 %res
}
; VBITS_GE_1024-NEXT: fmov w0, [[REDUCE]]
; VBITS_GE_1024-NEXT: ret
%op = load <32 x i32>, <32 x i32>* %a
- %res = call i32 @llvm.experimental.vector.reduce.or.v32i32(<32 x i32> %op)
+ %res = call i32 @llvm.vector.reduce.or.v32i32(<32 x i32> %op)
ret i32 %res
}
; VBITS_GE_2048-NEXT: fmov w0, [[REDUCE]]
; VBITS_GE_2048-NEXT: ret
%op = load <64 x i32>, <64 x i32>* %a
- %res = call i32 @llvm.experimental.vector.reduce.or.v64i32(<64 x i32> %op)
+ %res = call i32 @llvm.vector.reduce.or.v64i32(<64 x i32> %op)
ret i32 %res
}
; CHECK-LABEL: orv_v1i64:
; CHECK: fmov x0, d0
; CHECK: ret
- %res = call i64 @llvm.experimental.vector.reduce.or.v1i64(<1 x i64> %a)
+ %res = call i64 @llvm.vector.reduce.or.v1i64(<1 x i64> %a)
ret i64 %res
}
; CHECK: orv [[REDUCE:d[0-9]+]], [[PG]], z0.d
; CHECK: fmov x0, [[REDUCE]]
; CHECK: ret
- %res = call i64 @llvm.experimental.vector.reduce.or.v2i64(<2 x i64> %a)
+ %res = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> %a)
ret i64 %res
}
; CHECK-NEXT: fmov x0, [[REDUCE]]
; CHECK-NEXT: ret
%op = load <4 x i64>, <4 x i64>* %a
- %res = call i64 @llvm.experimental.vector.reduce.or.v4i64(<4 x i64> %op)
+ %res = call i64 @llvm.vector.reduce.or.v4i64(<4 x i64> %op)
ret i64 %res
}
; VBITS_EQ_256-NEXT: fmov x0, [[REDUCE]]
; VBITS_EQ_256-NEXT: ret
%op = load <8 x i64>, <8 x i64>* %a
- %res = call i64 @llvm.experimental.vector.reduce.or.v8i64(<8 x i64> %op)
+ %res = call i64 @llvm.vector.reduce.or.v8i64(<8 x i64> %op)
ret i64 %res
}
; VBITS_GE_1024-NEXT: fmov x0, [[REDUCE]]
; VBITS_GE_1024-NEXT: ret
%op = load <16 x i64>, <16 x i64>* %a
- %res = call i64 @llvm.experimental.vector.reduce.or.v16i64(<16 x i64> %op)
+ %res = call i64 @llvm.vector.reduce.or.v16i64(<16 x i64> %op)
ret i64 %res
}
; VBITS_GE_2048-NEXT: fmov x0, [[REDUCE]]
; VBITS_GE_2048-NEXT: ret
%op = load <32 x i64>, <32 x i64>* %a
- %res = call i64 @llvm.experimental.vector.reduce.or.v32i64(<32 x i64> %op)
+ %res = call i64 @llvm.vector.reduce.or.v32i64(<32 x i64> %op)
ret i64 %res
}
attributes #0 = { "target-features"="+sve" }
-declare i8 @llvm.experimental.vector.reduce.and.v8i8(<8 x i8>)
-declare i8 @llvm.experimental.vector.reduce.and.v16i8(<16 x i8>)
-declare i8 @llvm.experimental.vector.reduce.and.v32i8(<32 x i8>)
-declare i8 @llvm.experimental.vector.reduce.and.v64i8(<64 x i8>)
-declare i8 @llvm.experimental.vector.reduce.and.v128i8(<128 x i8>)
-declare i8 @llvm.experimental.vector.reduce.and.v256i8(<256 x i8>)
-
-declare i16 @llvm.experimental.vector.reduce.and.v4i16(<4 x i16>)
-declare i16 @llvm.experimental.vector.reduce.and.v8i16(<8 x i16>)
-declare i16 @llvm.experimental.vector.reduce.and.v16i16(<16 x i16>)
-declare i16 @llvm.experimental.vector.reduce.and.v32i16(<32 x i16>)
-declare i16 @llvm.experimental.vector.reduce.and.v64i16(<64 x i16>)
-declare i16 @llvm.experimental.vector.reduce.and.v128i16(<128 x i16>)
-
-declare i32 @llvm.experimental.vector.reduce.and.v2i32(<2 x i32>)
-declare i32 @llvm.experimental.vector.reduce.and.v4i32(<4 x i32>)
-declare i32 @llvm.experimental.vector.reduce.and.v8i32(<8 x i32>)
-declare i32 @llvm.experimental.vector.reduce.and.v16i32(<16 x i32>)
-declare i32 @llvm.experimental.vector.reduce.and.v32i32(<32 x i32>)
-declare i32 @llvm.experimental.vector.reduce.and.v64i32(<64 x i32>)
-
-declare i64 @llvm.experimental.vector.reduce.and.v1i64(<1 x i64>)
-declare i64 @llvm.experimental.vector.reduce.and.v2i64(<2 x i64>)
-declare i64 @llvm.experimental.vector.reduce.and.v4i64(<4 x i64>)
-declare i64 @llvm.experimental.vector.reduce.and.v8i64(<8 x i64>)
-declare i64 @llvm.experimental.vector.reduce.and.v16i64(<16 x i64>)
-declare i64 @llvm.experimental.vector.reduce.and.v32i64(<32 x i64>)
-
-declare i8 @llvm.experimental.vector.reduce.or.v8i8(<8 x i8>)
-declare i8 @llvm.experimental.vector.reduce.or.v16i8(<16 x i8>)
-declare i8 @llvm.experimental.vector.reduce.or.v32i8(<32 x i8>)
-declare i8 @llvm.experimental.vector.reduce.or.v64i8(<64 x i8>)
-declare i8 @llvm.experimental.vector.reduce.or.v128i8(<128 x i8>)
-declare i8 @llvm.experimental.vector.reduce.or.v256i8(<256 x i8>)
-
-declare i16 @llvm.experimental.vector.reduce.or.v4i16(<4 x i16>)
-declare i16 @llvm.experimental.vector.reduce.or.v8i16(<8 x i16>)
-declare i16 @llvm.experimental.vector.reduce.or.v16i16(<16 x i16>)
-declare i16 @llvm.experimental.vector.reduce.or.v32i16(<32 x i16>)
-declare i16 @llvm.experimental.vector.reduce.or.v64i16(<64 x i16>)
-declare i16 @llvm.experimental.vector.reduce.or.v128i16(<128 x i16>)
-
-declare i32 @llvm.experimental.vector.reduce.or.v2i32(<2 x i32>)
-declare i32 @llvm.experimental.vector.reduce.or.v4i32(<4 x i32>)
-declare i32 @llvm.experimental.vector.reduce.or.v8i32(<8 x i32>)
-declare i32 @llvm.experimental.vector.reduce.or.v16i32(<16 x i32>)
-declare i32 @llvm.experimental.vector.reduce.or.v32i32(<32 x i32>)
-declare i32 @llvm.experimental.vector.reduce.or.v64i32(<64 x i32>)
-
-declare i64 @llvm.experimental.vector.reduce.or.v1i64(<1 x i64>)
-declare i64 @llvm.experimental.vector.reduce.or.v2i64(<2 x i64>)
-declare i64 @llvm.experimental.vector.reduce.or.v4i64(<4 x i64>)
-declare i64 @llvm.experimental.vector.reduce.or.v8i64(<8 x i64>)
-declare i64 @llvm.experimental.vector.reduce.or.v16i64(<16 x i64>)
-declare i64 @llvm.experimental.vector.reduce.or.v32i64(<32 x i64>)
-
-declare i8 @llvm.experimental.vector.reduce.xor.v8i8(<8 x i8>)
-declare i8 @llvm.experimental.vector.reduce.xor.v16i8(<16 x i8>)
-declare i8 @llvm.experimental.vector.reduce.xor.v32i8(<32 x i8>)
-declare i8 @llvm.experimental.vector.reduce.xor.v64i8(<64 x i8>)
-declare i8 @llvm.experimental.vector.reduce.xor.v128i8(<128 x i8>)
-declare i8 @llvm.experimental.vector.reduce.xor.v256i8(<256 x i8>)
-
-declare i16 @llvm.experimental.vector.reduce.xor.v4i16(<4 x i16>)
-declare i16 @llvm.experimental.vector.reduce.xor.v8i16(<8 x i16>)
-declare i16 @llvm.experimental.vector.reduce.xor.v16i16(<16 x i16>)
-declare i16 @llvm.experimental.vector.reduce.xor.v32i16(<32 x i16>)
-declare i16 @llvm.experimental.vector.reduce.xor.v64i16(<64 x i16>)
-declare i16 @llvm.experimental.vector.reduce.xor.v128i16(<128 x i16>)
-
-declare i32 @llvm.experimental.vector.reduce.xor.v2i32(<2 x i32>)
-declare i32 @llvm.experimental.vector.reduce.xor.v4i32(<4 x i32>)
-declare i32 @llvm.experimental.vector.reduce.xor.v8i32(<8 x i32>)
-declare i32 @llvm.experimental.vector.reduce.xor.v16i32(<16 x i32>)
-declare i32 @llvm.experimental.vector.reduce.xor.v32i32(<32 x i32>)
-declare i32 @llvm.experimental.vector.reduce.xor.v64i32(<64 x i32>)
-
-declare i64 @llvm.experimental.vector.reduce.xor.v1i64(<1 x i64>)
-declare i64 @llvm.experimental.vector.reduce.xor.v2i64(<2 x i64>)
-declare i64 @llvm.experimental.vector.reduce.xor.v4i64(<4 x i64>)
-declare i64 @llvm.experimental.vector.reduce.xor.v8i64(<8 x i64>)
-declare i64 @llvm.experimental.vector.reduce.xor.v16i64(<16 x i64>)
-declare i64 @llvm.experimental.vector.reduce.xor.v32i64(<32 x i64>)
+declare i8 @llvm.vector.reduce.and.v8i8(<8 x i8>)
+declare i8 @llvm.vector.reduce.and.v16i8(<16 x i8>)
+declare i8 @llvm.vector.reduce.and.v32i8(<32 x i8>)
+declare i8 @llvm.vector.reduce.and.v64i8(<64 x i8>)
+declare i8 @llvm.vector.reduce.and.v128i8(<128 x i8>)
+declare i8 @llvm.vector.reduce.and.v256i8(<256 x i8>)
+
+declare i16 @llvm.vector.reduce.and.v4i16(<4 x i16>)
+declare i16 @llvm.vector.reduce.and.v8i16(<8 x i16>)
+declare i16 @llvm.vector.reduce.and.v16i16(<16 x i16>)
+declare i16 @llvm.vector.reduce.and.v32i16(<32 x i16>)
+declare i16 @llvm.vector.reduce.and.v64i16(<64 x i16>)
+declare i16 @llvm.vector.reduce.and.v128i16(<128 x i16>)
+
+declare i32 @llvm.vector.reduce.and.v2i32(<2 x i32>)
+declare i32 @llvm.vector.reduce.and.v4i32(<4 x i32>)
+declare i32 @llvm.vector.reduce.and.v8i32(<8 x i32>)
+declare i32 @llvm.vector.reduce.and.v16i32(<16 x i32>)
+declare i32 @llvm.vector.reduce.and.v32i32(<32 x i32>)
+declare i32 @llvm.vector.reduce.and.v64i32(<64 x i32>)
+
+declare i64 @llvm.vector.reduce.and.v1i64(<1 x i64>)
+declare i64 @llvm.vector.reduce.and.v2i64(<2 x i64>)
+declare i64 @llvm.vector.reduce.and.v4i64(<4 x i64>)
+declare i64 @llvm.vector.reduce.and.v8i64(<8 x i64>)
+declare i64 @llvm.vector.reduce.and.v16i64(<16 x i64>)
+declare i64 @llvm.vector.reduce.and.v32i64(<32 x i64>)
+
+declare i8 @llvm.vector.reduce.or.v8i8(<8 x i8>)
+declare i8 @llvm.vector.reduce.or.v16i8(<16 x i8>)
+declare i8 @llvm.vector.reduce.or.v32i8(<32 x i8>)
+declare i8 @llvm.vector.reduce.or.v64i8(<64 x i8>)
+declare i8 @llvm.vector.reduce.or.v128i8(<128 x i8>)
+declare i8 @llvm.vector.reduce.or.v256i8(<256 x i8>)
+
+declare i16 @llvm.vector.reduce.or.v4i16(<4 x i16>)
+declare i16 @llvm.vector.reduce.or.v8i16(<8 x i16>)
+declare i16 @llvm.vector.reduce.or.v16i16(<16 x i16>)
+declare i16 @llvm.vector.reduce.or.v32i16(<32 x i16>)
+declare i16 @llvm.vector.reduce.or.v64i16(<64 x i16>)
+declare i16 @llvm.vector.reduce.or.v128i16(<128 x i16>)
+
+declare i32 @llvm.vector.reduce.or.v2i32(<2 x i32>)
+declare i32 @llvm.vector.reduce.or.v4i32(<4 x i32>)
+declare i32 @llvm.vector.reduce.or.v8i32(<8 x i32>)
+declare i32 @llvm.vector.reduce.or.v16i32(<16 x i32>)
+declare i32 @llvm.vector.reduce.or.v32i32(<32 x i32>)
+declare i32 @llvm.vector.reduce.or.v64i32(<64 x i32>)
+
+declare i64 @llvm.vector.reduce.or.v1i64(<1 x i64>)
+declare i64 @llvm.vector.reduce.or.v2i64(<2 x i64>)
+declare i64 @llvm.vector.reduce.or.v4i64(<4 x i64>)
+declare i64 @llvm.vector.reduce.or.v8i64(<8 x i64>)
+declare i64 @llvm.vector.reduce.or.v16i64(<16 x i64>)
+declare i64 @llvm.vector.reduce.or.v32i64(<32 x i64>)
+
+declare i8 @llvm.vector.reduce.xor.v8i8(<8 x i8>)
+declare i8 @llvm.vector.reduce.xor.v16i8(<16 x i8>)
+declare i8 @llvm.vector.reduce.xor.v32i8(<32 x i8>)
+declare i8 @llvm.vector.reduce.xor.v64i8(<64 x i8>)
+declare i8 @llvm.vector.reduce.xor.v128i8(<128 x i8>)
+declare i8 @llvm.vector.reduce.xor.v256i8(<256 x i8>)
+
+declare i16 @llvm.vector.reduce.xor.v4i16(<4 x i16>)
+declare i16 @llvm.vector.reduce.xor.v8i16(<8 x i16>)
+declare i16 @llvm.vector.reduce.xor.v16i16(<16 x i16>)
+declare i16 @llvm.vector.reduce.xor.v32i16(<32 x i16>)
+declare i16 @llvm.vector.reduce.xor.v64i16(<64 x i16>)
+declare i16 @llvm.vector.reduce.xor.v128i16(<128 x i16>)
+
+declare i32 @llvm.vector.reduce.xor.v2i32(<2 x i32>)
+declare i32 @llvm.vector.reduce.xor.v4i32(<4 x i32>)
+declare i32 @llvm.vector.reduce.xor.v8i32(<8 x i32>)
+declare i32 @llvm.vector.reduce.xor.v16i32(<16 x i32>)
+declare i32 @llvm.vector.reduce.xor.v32i32(<32 x i32>)
+declare i32 @llvm.vector.reduce.xor.v64i32(<64 x i32>)
+
+declare i64 @llvm.vector.reduce.xor.v1i64(<1 x i64>)
+declare i64 @llvm.vector.reduce.xor.v2i64(<2 x i64>)
+declare i64 @llvm.vector.reduce.xor.v4i64(<4 x i64>)
+declare i64 @llvm.vector.reduce.xor.v8i64(<8 x i64>)
+declare i64 @llvm.vector.reduce.xor.v16i64(<16 x i64>)
+declare i64 @llvm.vector.reduce.xor.v32i64(<32 x i64>)