* sysdeps/unix/sysv/linux/mips/sys/tas.h (_test_and_set): Added memory

	barriers to enforce strict ordering on weakly ordered systems.

diff --git a/ChangeLog.mips b/ChangeLog.mips
index 711f23b..0ca16cc 100644 (file)
--- a/ChangeLog.mips
+++ b/ChangeLog.mips
@@ -1,3 +1,8 @@
+2008-03-27  Robin Randhawa  <robin@mips.com>
+
+       * sysdeps/unix/sysv/linux/mips/sys/tas.h (_test_and_set): Added memory
+       barriers to enforce strict ordering on weakly ordered systems.
+
 2008-03-26  David Stephenson  <david.stephenson@sicortex.com>
            Daniel Jacobowitz  <dan@codesourcery.com>
 

diff --git a/sysdeps/unix/sysv/linux/mips/sys/tas.h b/sysdeps/unix/sysv/linux/mips/sys/tas.h
index 309438d..b370ee4 100644 (file)
--- a/sysdeps/unix/sysv/linux/mips/sys/tas.h
+++ b/sysdeps/unix/sysv/linux/mips/sys/tas.h
@@ -40,17 +40,19 @@ __NTH (_test_and_set (int *p, int v))
 
   __asm__ __volatile__
     ("/* Inline test and set */\n"
-     "1:\n\t"
      ".set     push\n\t"
 #if _MIPS_SIM == _ABIO32
      ".set     mips2\n\t"
 #endif
+     "sync\n\t"
+     "1:\n\t"
      "ll       %0,%3\n\t"
      "move     %1,%4\n\t"
      "beq      %0,%4,2f\n\t"
      "sc       %1,%2\n\t"
-     ".set     pop\n\t"
      "beqz     %1,1b\n"
+     "sync\n\t"
+     ".set     pop\n\t"
      "2:\n\t"
      "/* End test and set */"
      : "=&r" (r), "=&r" (t), "=m" (*p)