/// Return the minimum required alignment in bytes for a spill slot for
/// a register of this class.
- unsigned getSpillAlignment(const TargetRegisterClass &RC) const {
- return getRegClassInfo(RC).SpillAlignment / 8;
- }
-
- /// Return the minimum required alignment in bytes for a spill slot for
- /// a register of this class.
Align getSpillAlign(const TargetRegisterClass &RC) const {
return Align(getRegClassInfo(RC).SpillAlignment / 8);
}
return true;
};
- auto UseAligned = [&] (const MachineInstr &MI, unsigned NeedAlign) {
+ auto UseAligned = [&](const MachineInstr &MI, Align NeedAlign) {
if (MI.memoperands().empty())
return false;
return all_of(MI.memoperands(), [NeedAlign](const MachineMemOperand *MMO) {
const MachineOperand &BaseOp = MI.getOperand(1);
assert(BaseOp.getSubReg() == 0);
int Offset = MI.getOperand(2).getImm();
- unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
+ Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
: Hexagon::V6_vL32Ub_ai;
BuildMI(MBB, MI, DL, get(NewOpc), DstReg)
assert(BaseOp.getSubReg() == 0);
int Offset = MI.getOperand(2).getImm();
unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
- unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
+ Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai
: Hexagon::V6_vL32Ub_ai;
BuildMI(MBB, MI, DL, get(NewOpc),
const MachineOperand &BaseOp = MI.getOperand(0);
assert(BaseOp.getSubReg() == 0);
int Offset = MI.getOperand(1).getImm();
- unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
+ Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
: Hexagon::V6_vS32Ub_ai;
BuildMI(MBB, MI, DL, get(NewOpc))
assert(BaseOp.getSubReg() == 0);
int Offset = MI.getOperand(1).getImm();
unsigned VecOffset = HRI.getSpillSize(Hexagon::HvxVRRegClass);
- unsigned NeedAlign = HRI.getSpillAlignment(Hexagon::HvxVRRegClass);
+ Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass);
unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai
: Hexagon::V6_vS32Ub_ai;
BuildMI(MBB, MI, DL, get(NewOpc))