octeontx2-af: cn10k: Use FLIT0 register instead of FLIT1

RVU SMMU widget stores the final translated PA at
RVU_AF_SMMU_TLN_FLIT0<57:18> instead of FLIT1 register. This patch
fixes the address translation logic to use the correct register.

Fixes: 893ae97214c3 ("octeontx2-af: cn10k: Support configurable LMTST regions")
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Signed-off-by: Sunil Goutham <sgoutham@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
index 28dcce7..dbe9149 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c
@@ -82,10 +82,10 @@ static int rvu_get_lmtaddr(struct rvu *rvu, u16 pcifunc,
                dev_err(rvu->dev, "%s LMTLINE iova transulation failed err:%llx\n", __func__, val);
                return -EIO;
        }
-       /* PA[51:12] = RVU_AF_SMMU_TLN_FLIT1[60:21]
+       /* PA[51:12] = RVU_AF_SMMU_TLN_FLIT0[57:18]
         * PA[11:0] = IOVA[11:0]
         */
-       pa = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_TLN_FLIT1) >> 21;
+       pa = rvu_read64(rvu, BLKADDR_RVUM, RVU_AF_SMMU_TLN_FLIT0) >> 18;
        pa &= GENMASK_ULL(39, 0);
        *lmt_addr = (pa << 12) | (iova  & 0xFFF);
 

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
index 6efcf3a..960ee1c 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.h
@@ -53,7 +53,7 @@
 #define RVU_AF_SMMU_TXN_REQ                (0x6008)
 #define RVU_AF_SMMU_ADDR_RSP_STS           (0x6010)
 #define RVU_AF_SMMU_ADDR_TLN               (0x6018)
-#define RVU_AF_SMMU_TLN_FLIT1              (0x6030)
+#define RVU_AF_SMMU_TLN_FLIT0              (0x6020)
 
 /* Admin function's privileged PF/VF registers */
 #define RVU_PRIV_CONST                      (0x8000000)