ARM: dts: rockchip: add power controller for RK322x

Add the power controller node and the correspondending qos nodes for
RK322x.
Also add the power-domain property to the nodes that are already
present.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20210527154455.358869-10-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm/boot/dts/rk322x.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index cffd7ac..ea8ceeb 100644 (file)
--- a/arch/arm/boot/dts/rk322x.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -6,6 +6,7 @@
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/clock/rk3228-cru.h>
 #include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/power/rk3228-power.h>
 
 / {
        #address-cells = <1>;
@@ -190,6 +191,64 @@
                        status = "disabled";
                };
 
+               power: power-controller {
+                       compatible = "rockchip,rk3228-power-controller";
+                       #power-domain-cells = <1>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       power-domain@RK3228_PD_VIO {
+                               reg = <RK3228_PD_VIO>;
+                               clocks = <&cru ACLK_HDCP>,
+                                        <&cru SCLK_HDCP>,
+                                        <&cru ACLK_IEP>,
+                                        <&cru HCLK_IEP>,
+                                        <&cru ACLK_RGA>,
+                                        <&cru HCLK_RGA>,
+                                        <&cru SCLK_RGA>;
+                               pm_qos = <&qos_hdcp>,
+                                        <&qos_iep>,
+                                        <&qos_rga_r>,
+                                        <&qos_rga_w>;
+                               #power-domain-cells = <0>;
+                       };
+
+                       power-domain@RK3228_PD_VOP {
+                               reg = <RK3228_PD_VOP>;
+                               clocks =<&cru ACLK_VOP>,
+                                       <&cru DCLK_VOP>,
+                                       <&cru HCLK_VOP>;
+                               pm_qos = <&qos_vop>;
+                               #power-domain-cells = <0>;
+                       };
+
+                       power-domain@RK3228_PD_VPU {
+                               reg = <RK3228_PD_VPU>;
+                               clocks = <&cru ACLK_VPU>,
+                                        <&cru HCLK_VPU>;
+                               pm_qos = <&qos_vpu>;
+                               #power-domain-cells = <0>;
+                       };
+
+                       power-domain@RK3228_PD_RKVDEC {
+                               reg = <RK3228_PD_RKVDEC>;
+                               clocks = <&cru ACLK_RKVDEC>,
+                                        <&cru HCLK_RKVDEC>,
+                                        <&cru SCLK_VDEC_CABAC>,
+                                        <&cru SCLK_VDEC_CORE>;
+                               pm_qos = <&qos_rkvdec_r>,
+                                        <&qos_rkvdec_w>;
+                               #power-domain-cells = <0>;
+                       };
+
+                       power-domain@RK3228_PD_GPU {
+                               reg = <RK3228_PD_GPU>;
+                               clocks = <&cru ACLK_GPU>;
+                               pm_qos = <&qos_gpu>;
+                               #power-domain-cells = <0>;
+                       };
+               };
+
                u2phy0: usb2phy@760 {
                        compatible = "rockchip,rk3228-usb2phy";
                        reg = <0x0760 0x0c>;
@@ -546,6 +605,7 @@
                                  "ppmmu1";
                clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
                clock-names = "bus", "core";
+               power-domains = <&power RK3228_PD_GPU>;
                resets = <&cru SRST_GPU_A>;
                status = "disabled";
        };
@@ -556,6 +616,7 @@
                interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
                clock-names = "aclk", "iface";
+               power-domains = <&power RK3228_PD_VPU>;
                #iommu-cells = <0>;
                status = "disabled";
        };
@@ -566,6 +627,7 @@
                interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
                clock-names = "aclk", "iface";
+               power-domains = <&power RK3228_PD_RKVDEC>;
                #iommu-cells = <0>;
                status = "disabled";
        };
@@ -579,6 +641,7 @@
                resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
                reset-names = "axi", "ahb", "dclk";
                iommus = <&vop_mmu>;
+               power-domains = <&power RK3228_PD_VOP>;
                status = "disabled";
 
                vop_out: port {
@@ -598,6 +661,7 @@
                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
                clock-names = "aclk", "iface";
+               power-domains = <&power RK3228_PD_VOP>;
                #iommu-cells = <0>;
                status = "disabled";
        };
@@ -608,6 +672,7 @@
                interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
                clock-names = "aclk", "hclk", "sclk";
+               power-domains = <&power RK3228_PD_VIO>;
                resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>;
                reset-names = "core", "axi", "ahb";
        };
@@ -618,6 +683,7 @@
                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
                clock-names = "aclk", "iface";
+               power-domains = <&power RK3228_PD_VIO>;
                #iommu-cells = <0>;
                status = "disabled";
        };
@@ -792,6 +858,51 @@
                status = "disabled";
        };
 
+       qos_iep: qos@31030080 {
+               compatible = "rockchip,rk3228-qos", "syscon";
+               reg = <0x31030080 0x20>;
+       };
+
+       qos_rga_w: qos@31030100 {
+               compatible = "rockchip,rk3228-qos", "syscon";
+               reg = <0x31030100 0x20>;
+       };
+
+       qos_hdcp: qos@31030180 {
+               compatible = "rockchip,rk3228-qos", "syscon";
+               reg = <0x31030180 0x20>;
+       };
+
+       qos_rga_r: qos@31030200 {
+               compatible = "rockchip,rk3228-qos", "syscon";
+               reg = <0x31030200 0x20>;
+       };
+
+       qos_vpu: qos@31040000 {
+               compatible = "rockchip,rk3228-qos", "syscon";
+               reg = <0x31040000 0x20>;
+       };
+
+       qos_gpu: qos@31050000 {
+               compatible = "rockchip,rk3228-qos", "syscon";
+               reg = <0x31050000 0x20>;
+       };
+
+       qos_vop: qos@31060000 {
+               compatible = "rockchip,rk3228-qos", "syscon";
+               reg = <0x31060000 0x20>;
+       };
+
+       qos_rkvdec_r: qos@31070000 {
+               compatible = "rockchip,rk3228-qos", "syscon";
+               reg = <0x31070000 0x20>;
+       };
+
+       qos_rkvdec_w: qos@31070080 {
+               compatible = "rockchip,rk3228-qos", "syscon";
+               reg = <0x31070080 0x20>;
+       };
+
        gic: interrupt-controller@32010000 {
                compatible = "arm,gic-400";
                interrupt-controller;