drm/i915: Simplify enabling user-interrupts with L3-remapping

Borrow the idea from intel_lrc.c to precompute the mask of interrupts we
wish to always enable to avoid having lots of conditionals inside the
interrupt enabling.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1467390209-3576-19-git-send-email-chris@chris-wilson.co.uk

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 994f761..a924a9f 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1313,8 +1313,7 @@ static int init_render_ring(struct intel_engine_cs *engine)
        if (IS_GEN(dev_priv, 6, 7))
                I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 
-       if (HAS_L3_DPF(dev_priv))
-               I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
+       I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
 
        return init_workarounds_ring(engine);
 }
@@ -1729,12 +1728,9 @@ gen6_irq_enable(struct intel_engine_cs *engine)
 {
        struct drm_i915_private *dev_priv = engine->i915;
 
-       if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
-               I915_WRITE_IMR(engine,
-                              ~(engine->irq_enable_mask |
-                                GT_PARITY_ERROR(dev_priv)));
-       else
-               I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
+       I915_WRITE_IMR(engine,
+                      ~(engine->irq_enable_mask |
+                        engine->irq_keep_mask));
        gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
 }
 
@@ -1743,10 +1739,7 @@ gen6_irq_disable(struct intel_engine_cs *engine)
 {
        struct drm_i915_private *dev_priv = engine->i915;
 
-       if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
-               I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev_priv));
-       else
-               I915_WRITE_IMR(engine, ~0);
+       I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
        gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
 }
 
@@ -1773,12 +1766,9 @@ gen8_irq_enable(struct intel_engine_cs *engine)
 {
        struct drm_i915_private *dev_priv = engine->i915;
 
-       if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
-               I915_WRITE_IMR(engine,
-                              ~(engine->irq_enable_mask |
-                                GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
-       else
-               I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
+       I915_WRITE_IMR(engine,
+                      ~(engine->irq_enable_mask |
+                        engine->irq_keep_mask));
        POSTING_READ_FW(RING_IMR(engine->mmio_base));
 }
 
@@ -1787,11 +1777,7 @@ gen8_irq_disable(struct intel_engine_cs *engine)
 {
        struct drm_i915_private *dev_priv = engine->i915;
 
-       if (HAS_L3_DPF(dev_priv) && engine->id == RCS)
-               I915_WRITE_IMR(engine,
-                              ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
-       else
-               I915_WRITE_IMR(engine, ~0);
+       I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
 }
 
 static int
@@ -2872,6 +2858,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
        intel_ring_default_vfuncs(dev_priv, engine);
 
        engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
+       if (HAS_L3_DPF(dev_priv))
+               engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
 
        if (INTEL_GEN(dev_priv) >= 8) {
                engine->init_context = intel_rcs_ctx_init;

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 3fdf2a0..41cc9f3 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -190,7 +190,8 @@ struct intel_engine_cs {
        struct i915_ctx_workarounds wa_ctx;
 
        bool            irq_posted;
-       u32             irq_enable_mask;        /* bitmask to enable ring interrupt */
+       u32             irq_keep_mask; /* always keep these interrupts */
+       u32             irq_enable_mask; /* bitmask to enable ring interrupt */
        void            (*irq_enable)(struct intel_engine_cs *ring);
        void            (*irq_disable)(struct intel_engine_cs *ring);
 
@@ -287,7 +288,6 @@ struct intel_engine_cs {
        unsigned int idle_lite_restore_wa;
        bool disable_lite_restore_wa;
        u32 ctx_desc_template;
-       u32             irq_keep_mask; /* bitmask for interrupts that should not be masked */
        int             (*emit_request)(struct drm_i915_gem_request *request);
        int             (*emit_flush)(struct drm_i915_gem_request *request,
                                      u32 invalidate_domains,