-; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=hard -O1 < %s | FileCheck %s
-; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=soft -O1 < %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=hard < %s | FileCheck %s --check-prefix=CHECKHARD
+; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=soft < %s | FileCheck %s --check-prefix=CHECKSOFT
define float @test_vget_lane_f16_1(<4 x half> %a) nounwind {
-; CHECK-LABEL: test_vget_lane_f16_1:
-; CHECK: vmovx.f16 s0, s0
-; CHECK-NEXT: vcvtb.f32.f16 s0, s0
+; CHECKHARD-LABEL: test_vget_lane_f16_1:
+; CHECKHARD: @ %bb.0: @ %entry
+; CHECKHARD-NEXT: vmovx.f16 s0, s0
+; CHECKHARD-NEXT: vcvtb.f32.f16 s0, s0
+; CHECKHARD-NEXT: bx lr
+;
+; CHECKSOFT-LABEL: test_vget_lane_f16_1:
+; CHECKSOFT: @ %bb.0: @ %entry
+; CHECKSOFT-NEXT: vmov d0, r0, r1
+; CHECKSOFT-NEXT: vmovx.f16 s0, s0
+; CHECKSOFT-NEXT: vcvtb.f32.f16 s0, s0
+; CHECKSOFT-NEXT: vmov r0, s0
+; CHECKSOFT-NEXT: bx lr
entry:
%elt = extractelement <4 x half> %a, i32 1
%conv = fpext half %elt to float
}
define float @test_vget_lane_f16_2(<4 x half> %a) nounwind {
-; CHECK-LABEL: test_vget_lane_f16_2:
-; CHECK-NOT: vmovx.f16
-; CHECK: vcvtb.f32.f16 s0, s1
+; CHECKHARD-LABEL: test_vget_lane_f16_2:
+; CHECKHARD: @ %bb.0: @ %entry
+; CHECKHARD-NEXT: vcvtb.f32.f16 s0, s1
+; CHECKHARD-NEXT: bx lr
+;
+; CHECKSOFT-LABEL: test_vget_lane_f16_2:
+; CHECKSOFT: @ %bb.0: @ %entry
+; CHECKSOFT-NEXT: vmov d0, r0, r1
+; CHECKSOFT-NEXT: vcvtb.f32.f16 s0, s1
+; CHECKSOFT-NEXT: vmov r0, s0
+; CHECKSOFT-NEXT: bx lr
entry:
%elt = extractelement <4 x half> %a, i32 2
%conv = fpext half %elt to float
}
define float @test_vget_laneq_f16_6(<8 x half> %a) nounwind {
-; CHECK-LABEL: test_vget_laneq_f16_6:
-; CHECK-NOT: vmovx.f16
-; CHECK: vcvtb.f32.f16 s0, s3
+; CHECKHARD-LABEL: test_vget_laneq_f16_6:
+; CHECKHARD: @ %bb.0: @ %entry
+; CHECKHARD-NEXT: vcvtb.f32.f16 s0, s3
+; CHECKHARD-NEXT: bx lr
+;
+; CHECKSOFT-LABEL: test_vget_laneq_f16_6:
+; CHECKSOFT: @ %bb.0: @ %entry
+; CHECKSOFT-NEXT: vmov d1, r2, r3
+; CHECKSOFT-NEXT: vcvtb.f32.f16 s0, s3
+; CHECKSOFT-NEXT: vmov r0, s0
+; CHECKSOFT-NEXT: bx lr
entry:
%elt = extractelement <8 x half> %a, i32 6
%conv = fpext half %elt to float
}
define float @test_vget_laneq_f16_7(<8 x half> %a) nounwind {
-; CHECK-LABEL: test_vget_laneq_f16_7:
-; CHECK: vmovx.f16 s0, s3
-; CHECK: vcvtb.f32.f16 s0, s0
+; CHECKHARD-LABEL: test_vget_laneq_f16_7:
+; CHECKHARD: @ %bb.0: @ %entry
+; CHECKHARD-NEXT: vmovx.f16 s0, s3
+; CHECKHARD-NEXT: vcvtb.f32.f16 s0, s0
+; CHECKHARD-NEXT: bx lr
+;
+; CHECKSOFT-LABEL: test_vget_laneq_f16_7:
+; CHECKSOFT: @ %bb.0: @ %entry
+; CHECKSOFT-NEXT: vmov d1, r2, r3
+; CHECKSOFT-NEXT: vmovx.f16 s0, s3
+; CHECKSOFT-NEXT: vcvtb.f32.f16 s0, s0
+; CHECKSOFT-NEXT: vmov r0, s0
+; CHECKSOFT-NEXT: bx lr
entry:
%elt = extractelement <8 x half> %a, i32 7
%conv = fpext half %elt to float
}
define <4 x half> @test_vset_lane_f16(<4 x half> %a, float %fb) nounwind {
-; CHECK-LABEL: test_vset_lane_f16:
-; CHECK: vmov.f16 r[[GPR:[0-9]+]], s{{[0-9]+}}
-; CHECK: vmov.16 d{{[0-9]+}}[3], r[[GPR]]
+; CHECKHARD-LABEL: test_vset_lane_f16:
+; CHECKHARD: @ %bb.0: @ %entry
+; CHECKHARD-NEXT: vcvtb.f16.f32 s2, s2
+; CHECKHARD-NEXT: vmov.f16 r0, s2
+; CHECKHARD-NEXT: vmov.16 d0[3], r0
+; CHECKHARD-NEXT: bx lr
+;
+; CHECKSOFT-LABEL: test_vset_lane_f16:
+; CHECKSOFT: @ %bb.0: @ %entry
+; CHECKSOFT-NEXT: vmov s0, r2
+; CHECKSOFT-NEXT: vcvtb.f16.f32 s0, s0
+; CHECKSOFT-NEXT: vmov d16, r0, r1
+; CHECKSOFT-NEXT: vmov.f16 r2, s0
+; CHECKSOFT-NEXT: vmov.16 d16[3], r2
+; CHECKSOFT-NEXT: vmov r0, r1, d16
+; CHECKSOFT-NEXT: bx lr
entry:
%b = fptrunc float %fb to half
%x = insertelement <4 x half> %a, half %b, i32 3
}
define <8 x half> @test_vset_laneq_f16_1(<8 x half> %a, float %fb) nounwind {
-; CHECK-LABEL: test_vset_laneq_f16_1:
-; CHECK: vmov.f16 r[[GPR:[0-9]+]], s{{[0-9]+}}
-; CHECK: vmov.16 d{{[0-9]+}}[1], r[[GPR]]
+; CHECKHARD-LABEL: test_vset_laneq_f16_1:
+; CHECKHARD: @ %bb.0: @ %entry
+; CHECKHARD-NEXT: vcvtb.f16.f32 s4, s4
+; CHECKHARD-NEXT: vmov.f16 r0, s4
+; CHECKHARD-NEXT: vmov.16 d0[1], r0
+; CHECKHARD-NEXT: bx lr
+;
+; CHECKSOFT-LABEL: test_vset_laneq_f16_1:
+; CHECKSOFT: @ %bb.0: @ %entry
+; CHECKSOFT-NEXT: vldr s0, [sp]
+; CHECKSOFT-NEXT: vmov d17, r2, r3
+; CHECKSOFT-NEXT: vmov d16, r0, r1
+; CHECKSOFT-NEXT: vcvtb.f16.f32 s0, s0
+; CHECKSOFT-NEXT: vmov.f16 r12, s0
+; CHECKSOFT-NEXT: vmov.16 d16[1], r12
+; CHECKSOFT-NEXT: vmov r2, r3, d17
+; CHECKSOFT-NEXT: vmov r0, r1, d16
+; CHECKSOFT-NEXT: bx lr
entry:
%b = fptrunc float %fb to half
%x = insertelement <8 x half> %a, half %b, i32 1
}
define <8 x half> @test_vset_laneq_f16_7(<8 x half> %a, float %fb) nounwind {
-; CHECK-LABEL: test_vset_laneq_f16_7:
-; CHECK: vmov.f16 r[[GPR:[0-9]+]], s{{[0-9]+}}
-; CHECK: vmov.16 d{{[0-9]+}}[3], r[[GPR]]
+; CHECKHARD-LABEL: test_vset_laneq_f16_7:
+; CHECKHARD: @ %bb.0: @ %entry
+; CHECKHARD-NEXT: vcvtb.f16.f32 s4, s4
+; CHECKHARD-NEXT: vmov.f16 r0, s4
+; CHECKHARD-NEXT: vmov.16 d1[3], r0
+; CHECKHARD-NEXT: bx lr
+;
+; CHECKSOFT-LABEL: test_vset_laneq_f16_7:
+; CHECKSOFT: @ %bb.0: @ %entry
+; CHECKSOFT-NEXT: vldr s0, [sp]
+; CHECKSOFT-NEXT: vmov d17, r2, r3
+; CHECKSOFT-NEXT: vmov d16, r0, r1
+; CHECKSOFT-NEXT: vcvtb.f16.f32 s0, s0
+; CHECKSOFT-NEXT: vmov.f16 r12, s0
+; CHECKSOFT-NEXT: vmov.16 d17[3], r12
+; CHECKSOFT-NEXT: vmov r0, r1, d16
+; CHECKSOFT-NEXT: vmov r2, r3, d17
+; CHECKSOFT-NEXT: bx lr
entry:
%b = fptrunc float %fb to half
%x = insertelement <8 x half> %a, half %b, i32 7