; 64-CMP: addiu $2, $zero, 0
-; MM-DAG: lui $2, 0
+; MM-DAG: li16 $2, 0
%1 = fcmp false float %a, %b
%2 = zext i1 %1 to i32
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.eq.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ule.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ult.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.olt.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ole.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ueq.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.un.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ueq.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ole.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.olt.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ult.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ule.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.eq.s $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.un.s $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; 64-CMP: addiu $2, $zero, 0
-; MM-DAG: lui $2, 0
+; MM-DAG: li16 $2, 0
%1 = fcmp false double %a, %b
%2 = zext i1 %1 to i32
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.eq.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ule.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ult.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.olt.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ole.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ueq.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.un.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ueq.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ole.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.olt.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ult.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.ule.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.eq.d $f12, $f14
; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
-; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0
; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
; MM32R3-DAG: c.un.d $f12, $f14
; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
; GP64: addiu $2, $zero, 0
- ; MM: lui $2, 0
+ ; MM: li16 $2, 0
%r = and i1 4, %b
ret i1 %r
; GP64: andi $2, $4, 4
; MM32: andi16 $3, $5, 4
- ; MM32: lui $2, 0
+ ; MM32: li16 $2, 0
; MM64: andi $2, $4, 4
; GP64: daddiu $2, $zero, 0
; MM32: andi16 $5, $7, 4
- ; MM32: lui $2, 0
- ; MM32: lui $3, 0
- ; MM32: lui $4, 0
+ ; MM32: li16 $2, 0
+ ; MM32: li16 $3, 0
+ ; MM32: li16 $4, 0
; MM64: andi $3, $5, 4
; MM64: daddiu $2, $zero, 0
; GP64: andi $2, $4, 31
; MM32: andi16 $3, $5, 31
- ; MM32: lui $2, 0
+ ; MM32: li16 $2, 0
; MM64: andi $2, $4, 31
; GP64: daddiu $2, $zero, 0
; MM32: andi16 $5, $7, 31
- ; MM32: lui $2, 0
- ; MM32: lui $3, 0
- ; MM32: lui $4, 0
+ ; MM32: li16 $2, 0
+ ; MM32: li16 $3, 0
+ ; MM32: li16 $4, 0
; MM64: andi $3, $5, 31
; MM64: daddiu $2, $zero, 0
; GP64: andi $2, $4, 255
; MM32: andi16 $3, $5, 255
- ; MM32: lui $2, 0
+ ; MM32: li16 $2, 0
; MM64: andi $2, $4, 255
; GP64: daddiu $2, $zero, 0
; MM32: andi16 $5, $7, 255
- ; MM32: lui $2, 0
- ; MM32: lui $3, 0
- ; MM32: lui $4, 0
+ ; MM32: li16 $2, 0
+ ; MM32: li16 $3, 0
+ ; MM32: li16 $4, 0
; MM64: andi $3, $5, 255
; MM64: daddiu $2, $zero, 0
; GP64: addiu $2, $zero, 0
- ; MM: lui $2, 0
+ ; MM: li16 $2, 0
%r = and i1 32768, %b
ret i1 %r
; GP64: addiu $2, $zero, 0
- ; MM: lui $2, 0
+ ; MM: li16 $2, 0
%r = and i8 32768, %b
ret i8 %r
; GP64: andi $2, $4, 32768
; MM32: andi16 $3, $5, 32768
- ; MM32: lui $2, 0
+ ; MM32: li16 $2, 0
; MM64: andi $2, $4, 32768
; GP64: daddiu $2, $zero, 0
; MM32: andi16 $5, $7, 32768
- ; MM32: lui $2, 0
- ; MM32: lui $3, 0
- ; MM32: lui $4, 0
+ ; MM32: li16 $2, 0
+ ; MM32: li16 $3, 0
+ ; MM32: li16 $4, 0
; MM64: andi $3, $5, 32768
; MM64: daddiu $2, $zero, 0
; GP64: andi $2, $4, 65
- ; MM32: andi $3, $5, 65
- ; MM32: lui $2, 0
+ ; MM32-DAG: andi $3, $5, 65
+ ; MM32-DAG: li16 $2, 0
; MM64: andi $2, $4, 65
; GP64: andi $3, $5, 65
; GP64: daddiu $2, $zero, 0
- ; MM32: andi $5, $7, 65
- ; MM32: lui $2, 0
- ; MM32: lui $3, 0
- ; MM32: lui $4, 0
+ ; MM32-DAG: andi $5, $7, 65
+ ; MM32-DAG: li16 $2, 0
+ ; MM32-DAG: li16 $3, 0
+ ; MM32-DAG: li16 $4, 0
; MM64: andi $3, $5, 65
; MM64: daddiu $2, $zero, 0
; GP64: addiu $2, $zero, 0
- ; MM: lui $2, 0
+ ; MM: li16 $2, 0
%r = and i1 256, %b
ret i1 %r
; GP64: addiu $2, $zero, 0
- ; MM: lui $2, 0
+ ; MM: li16 $2, 0
%r = and i8 256, %b
ret i8 %r
; GP64: andi $2, $4, 256
- ; MM32: andi $3, $5, 256
- ; MM32: lui $2, 0
+ ; MM32-DAG: andi $3, $5, 256
+ ; MM32-DAG: li16 $2, 0
; MM64: andi $2, $4, 256
; GP64: andi $3, $5, 256
; GP64: daddiu $2, $zero, 0
- ; MM32: andi $5, $7, 256
- ; MM32: lui $2, 0
- ; MM32: lui $3, 0
- ; MM32: lui $4, 0
+ ; MM32-DAG: andi $5, $7, 256
+ ; MM32-DAG: li16 $2, 0
+ ; MM32-DAG: li16 $3, 0
+ ; MM32-DAG: li16 $4, 0
; MM64: andi $3, $5, 256
; MM64: daddiu $2, $zero, 0