radv: do not need to force emit the TCS regs on Vega20
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Wed, 1 May 2019 14:10:44 +0000 (16:10 +0200)
committerSamuel Pitoiset <samuel.pitoiset@gmail.com>
Thu, 2 May 2019 07:24:05 +0000 (09:24 +0200)
This chip doesn't need the fixup. This fixes a bunch of
dEQP-VK.tessellation tests and avoid random GPU hangs.

Cc: "19.0" "19.1" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
src/amd/vulkan/radv_nir_to_llvm.c

index adf158e..b4a19aa 100644 (file)
@@ -3691,6 +3691,7 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
                ac_init_exec_full_mask(&ctx.ac);
 
        if (ctx.ac.chip_class == GFX9 &&
+           ctx.ac.family != CHIP_VEGA20 &&
            shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
                ac_nir_fixup_ls_hs_input_vgprs(&ctx);