For the cover letter of this patch-set, please checkout D146872.
Depends on D147916.
This is the 11th patch of the patch-set.
This patch is a proof-of-concept and will be extended to full coverage
in the future. Only vset for tuple type of NF=2, EEW=32, LMUL=1 is
defined now.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D147917
let Name = "vset_v", Log2LMUL = [0, 1, 2], MaskedPolicyScheme = NonePolicy,
ManualCodegen = [{
{
+ if (isa<StructType>(ResultType)) // For tuple type
+ // Insert value (operand 2) into index (operand 1) of vtuple (operand 0)
+ return Builder.CreateInsertValue(
+ Ops[0], Ops[2],
+ {(unsigned)cast<ConstantInt>(Ops[1])->getZExtValue()});
auto *ResVecTy = cast<ScalableVectorType>(ResultType);
auto *VecTy = cast<ScalableVectorType>(Ops[2]->getType());
// Mask to only valid indices.
def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "v" # dst_lmul # "vKzv", "csilxfd">;
def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "Uv" # dst_lmul #"UvKzUv", "csil">;
}
+ foreach nf = [2] in {
+ let Log2LMUL = [0] in {
+ defvar T = "(Tuple:" # nf # ")";
+ def : RVVBuiltin<T # "vv", T # "v" # T # "vKzv", "i", "v">;
+ }
+ }
}
}
ASTContext::BuiltinVectorTypeInfo VecInfo =
Context.getBuiltinVectorTypeInfo(cast<BuiltinType>(
TheCall->getArg(2)->getType().getCanonicalType().getTypePtr()));
- unsigned MaxIndex =
- (ResVecInfo.EC.getKnownMinValue() * ResVecInfo.NumVectors) /
- (VecInfo.EC.getKnownMinValue() * VecInfo.NumVectors);
+ unsigned MaxIndex;
+ if (ResVecInfo.NumVectors != 1) // vset for tuple type
+ MaxIndex = ResVecInfo.NumVectors;
+ else // vset fo non-tuple type
+ MaxIndex = (ResVecInfo.EC.getKnownMinValue() * ResVecInfo.NumVectors) /
+ (VecInfo.EC.getKnownMinValue() * VecInfo.NumVectors);
return SemaBuiltinConstantArgRange(TheCall, 1, 0, MaxIndex - 1);
}
case RISCVVector::BI__builtin_rvv_sf_vc_i_se_u8mf8:
--- /dev/null
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN: FileCheck --check-prefix=CHECK-RV64 %s
+
+#include <riscv_vector.h>
+
+// CHECK-RV64-LABEL: define dso_local { <vscale x 2 x i32>, <vscale x 2 x i32> } @test_vset_v_i32m1x2_i32m1
+// CHECK-RV64-SAME: (<vscale x 2 x i32> [[DEST_COERCE0:%.*]], <vscale x 2 x i32> [[DEST_COERCE1:%.*]], <vscale x 2 x i32> [[VAL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT: entry:
+// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } poison, <vscale x 2 x i32> [[DEST_COERCE0]], 0
+// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP0]], <vscale x 2 x i32> [[DEST_COERCE1]], 1
+// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP1]], <vscale x 2 x i32> [[VAL]], 0
+// CHECK-RV64-NEXT: ret { <vscale x 2 x i32>, <vscale x 2 x i32> } [[TMP2]]
+//
+vint32m1x2_t test_vset_v_i32m1x2_i32m1(vint32m1x2_t dest, vint32m1_t val) {
+ return __riscv_vset_v_i32m1x2_i32m1(dest, 0, val);
+}
// expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
return __riscv_vset_v_f16m4_f16m8(dest, 2, val);
}
+
+vint32m1x2_t test_vset_v_i32m1x2_i32m1(vint32m1x2_t dest, vint32m1_t val) {
+ // expected-error@+1 {{argument value 2 is outside the valid range [0, 1]}}
+ return __riscv_vset_v_i32m1x2_i32m1(dest, 2, val);
+}