config: Add Chameleonv3 config

Add defconfig and Kconfig files for Google Chameleon V3 board

Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 547e47ed9df03c430ab6e32f4d344603c69e84ed..df44530e83ab0ab71c51a67d39030cbb9641c92e 100644 (file)
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -143,6 +143,10 @@ config TARGET_SOCFPGA_ARRIA5_SOCDK
        bool "Altera SOCFPGA SoCDK (Arria V)"
        select TARGET_SOCFPGA_ARRIA5
 
+config TARGET_SOCFPGA_CHAMELEONV3
+       bool "Google Chameleon v3 (Arria 10)"
+       select TARGET_SOCFPGA_ARRIA10
+
 config TARGET_SOCFPGA_CYCLONE5_SOCDK
        bool "Altera SOCFPGA SoCDK (Cyclone V)"
        select TARGET_SOCFPGA_CYCLONE5
@@ -198,6 +202,7 @@ config SYS_BOARD
        default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
        default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
        default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
+       default "chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
        default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
        default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
        default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@@ -224,6 +229,7 @@ config SYS_VENDOR
        default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
        default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
        default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
+       default "google" if TARGET_SOCFPGA_CHAMELEONV3
        default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
        default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
        default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@@ -240,6 +246,7 @@ config SYS_CONFIG_NAME
        default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
        default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
        default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
+       default "socfpga_chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
        default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
        default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
        default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO

diff --git a/configs/socfpga_chameleonv3_defconfig b/configs/socfpga_chameleonv3_defconfig
new file mode 100644 (file)
index 0000000..7870d31
--- /dev/null
+++ b/configs/socfpga_chameleonv3_defconfig
@@ -0,0 +1,29 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_chameleonv3_480_2"
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_FS_LOADER=y
+CONFIG_SPL_FS_LOADER=y
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_FPGA=y
+CONFIG_SPL_TEXT_BASE=0xFFE00000
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x4400
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_DESIGNWARE_APB_TIMER=y
+CONFIG_MMC_DW=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_MISC=y
+CONFIG_MISC_INIT_R=y
+CONFIG_ATSHA204A=y

diff --git a/include/configs/socfpga_chameleonv3.h b/include/configs/socfpga_chameleonv3.h
new file mode 100644 (file)
index 0000000..891b762
--- /dev/null
+++ b/include/configs/socfpga_chameleonv3.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2022 Google LLC
+ */
+#ifndef __SOCFGPA_CHAMELEONV3_H__
+#define __SOCFGPA_CHAMELEONV3_H__
+
+#include <asm/arch/base_addr_a10.h>
+
+#define CONFIG_SYS_BOOTM_LEN   (32 * 1024 * 1024)
+
+/*
+ * U-Boot general configurations
+ */
+
+/* Memory configurations  */
+#define PHYS_SDRAM_1_SIZE              0x40000000
+
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       "autoload=no\0" \
+       "bootargs=cma=256M console=ttyS1,115200 root=/dev/mmcblk0p3 rw rootwait\0" \
+       "distro_bootcmd=bridge enable; run bootcmd_mmc\0" \
+       "bootcmd_mmc=load mmc 0:1 ${loadaddr} kernel.itb; bootm\0" \
+       "bootcmd_net=dhcp; tftpboot ${loadaddr} kernel.itb; bootm\0"
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL                 0xFFFFFFFF
+
+/* SPL memory allocation configuration, this is for FAT implementation */
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x00015000
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif /* __SOCFGPA_CHAMELEONV3_H__ */