net: ethernet: mtk_eth_soc: reset PCS state
authorDaniel Golle <daniel@makrotopia.org>
Tue, 14 Mar 2023 00:34:26 +0000 (00:34 +0000)
committerDavid S. Miller <davem@davemloft.net>
Wed, 15 Mar 2023 08:58:13 +0000 (08:58 +0000)
Reset the internal PCS state machine when changing interface mode.
This prevents confusing the state machine when changing interface
modes, e.g. from SGMII to 2500Base-X or vice-versa.

Fixes: 7e538372694b ("net: ethernet: mediatek: Re-add support SGMII")
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Tested-by: Bjørn Mork <bjorn@mork.no>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/mediatek/mtk_eth_soc.h
drivers/net/ethernet/mediatek/mtk_sgmii.c

index b65de17..084a6ba 100644 (file)
 #define SGMII_SEND_AN_ERROR_EN         BIT(11)
 #define SGMII_IF_MODE_MASK             GENMASK(5, 1)
 
+/* Register to reset SGMII design */
+#define SGMII_RESERVED_0       0x34
+#define SGMII_SW_RESET         BIT(0)
+
 /* Register to set SGMII speed, ANA RG_ Control Signals III*/
 #define SGMSYS_ANA_RG_CS3      0x2028
 #define RG_PHY_SPEED_MASK      (BIT(2) | BIT(3))
index bb00de1..612f65b 100644 (file)
@@ -88,6 +88,10 @@ static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
                regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
                                   SGMII_PHYA_PWD, SGMII_PHYA_PWD);
 
+               /* Reset SGMII PCS state */
+               regmap_update_bits(mpcs->regmap, SGMII_RESERVED_0,
+                                  SGMII_SW_RESET, SGMII_SW_RESET);
+
                if (interface == PHY_INTERFACE_MODE_2500BASEX)
                        rgc3 = RG_PHY_SPEED_3_125G;
                else