#define TRANS_VSYNC_A 0xe0014
#define TRANS_VSYNC_END_SHIFT 16
#define TRANS_VSYNC_START_SHIFT 0
+#define TRANS_VSYNCSHIFT_A 0xe0028
#define TRANSA_DATA_M1 0xe0030
#define TRANSA_DATA_N1 0xe0034
#define TRANS_VTOTAL_B 0xe100c
#define TRANS_VBLANK_B 0xe1010
#define TRANS_VSYNC_B 0xe1014
+#define TRANS_VSYNCSHIFT_B 0xe1028
#define TRANSB_DATA_M1 0xe1030
#define TRANSB_DATA_N1 0xe1034
#define TRANS_VTOTAL_C 0xe200c
#define TRANS_VBLANK_C 0xe2010
#define TRANS_VSYNC_C 0xe2014
+#define TRANS_VSYNCSHIFT_C 0xe2028
#define TRANSC_DATA_M1 0xe2030
#define TRANSC_DATA_N1 0xe2034
DEFINEREG2(TRANS_VTOTAL_A, i830_debug_hvtotal),
DEFINEREG2(TRANS_VBLANK_A, i830_debug_hvsyncblank),
DEFINEREG2(TRANS_VSYNC_A, i830_debug_hvsyncblank),
+ DEFINEREG(TRANS_VSYNCSHIFT_A),
DEFINEREG2(TRANSA_DATA_M1, ironlake_debug_m_tu),
DEFINEREG2(TRANSA_DATA_N1, ironlake_debug_n),
DEFINEREG2(TRANS_VTOTAL_B, i830_debug_hvtotal),
DEFINEREG2(TRANS_VBLANK_B, i830_debug_hvsyncblank),
DEFINEREG2(TRANS_VSYNC_B, i830_debug_hvsyncblank),
+ DEFINEREG(TRANS_VSYNCSHIFT_B),
DEFINEREG2(TRANSB_DATA_M1, ironlake_debug_m_tu),
DEFINEREG2(TRANSB_DATA_N1, ironlake_debug_n),
DEFINEREG2(TRANS_VTOTAL_C, i830_debug_hvtotal),
DEFINEREG2(TRANS_VBLANK_C, i830_debug_hvsyncblank),
DEFINEREG2(TRANS_VSYNC_C, i830_debug_hvsyncblank),
+ DEFINEREG(TRANS_VSYNCSHIFT_C),
DEFINEREG2(TRANSC_DATA_M1, ironlake_debug_m_tu),
DEFINEREG2(TRANSC_DATA_N1, ironlake_debug_n),