/*
* The crystal freq used in calculations in this driver will be
* 28.636360 MHz.
- * Aim to run the PLLs' VCOs near 400 MHz to minimze errors.
+ * Aim to run the PLLs' VCOs near 400 MHz to minimize errors.
*/
/*
cx18_av_write4_expect(cx, CXADEC_DL_CTL, 0x03000000,
0x03000000, 0x13000000);
- /* initallize the PLL by toggling sleep bit */
+ /* initialize the PLL by toggling sleep bit */
v = cx18_av_read4(cx, CXADEC_HOST_REG1);
/* enable sleep mode - register appears to be read only... */
cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v | 1, v, 0xfffe);