hdmirx: enable hdcp2.2 for tm2 [1/2]
authoryicheng shen <yicheng.shen@amlogic.com>
Mon, 29 Apr 2019 09:15:01 +0000 (05:15 -0400)
committerTao Zeng <tao.zeng@amlogic.com>
Tue, 30 Apr 2019 09:22:13 +0000 (02:22 -0700)
PD#SWPL-7865

Problem:
TM2 hdcp2.2 can not work,esm bootup fail

Solution:
Enable Enable axi_clk.

Verify:
TM2

Change-Id: I44af6f2b5bfbe72cfdb93e1b42c47cda9c56d3a2
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_drv.h
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_hw.c

index 96b90c7..d924077 100644 (file)
@@ -41,7 +41,7 @@
  *
  *
  */
-#define RX_VER1 "ver.2019/04/22"
+#define RX_VER1 "ver.2019/04/29"
 /*
  *
  *
index 9e9aff7..082b31d 100644 (file)
@@ -1733,6 +1733,13 @@ void hdcp22_clk_en(bool en)
                else
                        /* TL1:esm related clk bit3-5 */
                        hdmirx_wr_bits_top(TOP_CLK_CNTL, MSK(3, 3), 0x7);
+
+               if (rx.chip_id >= CHIP_ID_TM2)
+                       /* Enable axi_clk,for tm2 */
+                       /* AXI arbiter is moved outside of hdmitx. */
+                       /* There is an AXI arbiter in the chip’s EE domain */
+                       /* for arbitrating AXI requests from HDMI TX and RX.*/
+                       hdmirx_wr_bits_top(TOP_CLK_CNTL, MSK(1, 12), 0x1);
        } else {
                hdmirx_wr_bits_top(TOP_CLK_CNTL, MSK(3, 3), 0x0);
                wr_reg_hhi(HHI_HDCP22_CLK_CNTL, 0);