Reset ARM cp15.c1_sys to default values. Fix XScale cp15 accesses.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3013 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 80727bb..1c748e2 100644 (file)
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -83,6 +83,7 @@ typedef struct CPUARMState {
         uint32_t c0_cachetype;
         uint32_t c1_sys; /* System control register.  */
         uint32_t c1_coproc; /* Coprocessor access register.  */
+        uint32_t c1_xscaleauxcr; /* XScale auxiliary control register.  */
         uint32_t c2_base; /* MMU translation table base.  */
         uint32_t c2_data; /* MPU data cachable bits.  */
         uint32_t c2_insn; /* MPU instruction cachable bits.  */

diff --git a/target-arm/helper.c b/target-arm/helper.c
index e8a2169..61f8109 100644 (file)
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -18,16 +18,19 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
         set_feature(env, ARM_FEATURE_VFP);
         env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
         env->cp15.c0_cachetype = 0x1dd20d2;
+        env->cp15.c1_sys = 0x00090078;
         break;
     case ARM_CPUID_ARM946:
         set_feature(env, ARM_FEATURE_MPU);
         env->cp15.c0_cachetype = 0x0f004006;
+        env->cp15.c1_sys = 0x00000078;
         break;
     case ARM_CPUID_ARM1026:
         set_feature(env, ARM_FEATURE_VFP);
         set_feature(env, ARM_FEATURE_AUXCR);
         env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
         env->cp15.c0_cachetype = 0x1dd20d2;
+        env->cp15.c1_sys = 0x00090078;
         break;
     case ARM_CPUID_PXA250:
     case ARM_CPUID_PXA255:
@@ -37,6 +40,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
         set_feature(env, ARM_FEATURE_XSCALE);
         /* JTAG_ID is ((id << 28) | 0x09265013) */
         env->cp15.c0_cachetype = 0xd172172;
+        env->cp15.c1_sys = 0x00000078;
         break;
     case ARM_CPUID_PXA270_A0:
     case ARM_CPUID_PXA270_A1:
@@ -49,6 +53,7 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
         set_feature(env, ARM_FEATURE_IWMMXT);
         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
         env->cp15.c0_cachetype = 0xd172172;
+        env->cp15.c1_sys = 0x00000078;
         break;
     default:
         cpu_abort(env, "Bad CPU ID: %x\n", id);
@@ -637,6 +642,8 @@ void helper_set_cp15(CPUState *env, uint32_t insn, uint32_t val)
     crm = insn & 0xf;
     switch ((insn >> 16) & 0xf) {
     case 0: /* ID codes.  */
+        if (arm_feature(env, ARM_FEATURE_XSCALE))
+            break;
         goto bad_reg;
     case 1: /* System configuration.  */
         switch (op2) {
@@ -648,12 +655,14 @@ void helper_set_cp15(CPUState *env, uint32_t insn, uint32_t val)
             tlb_flush(env, 1);
             break;
         case 1:
-            /* XScale doesn't implement AUX CR (P-Bit) but allows
-             * writing with zero and reading.  */
-            if (arm_feature(env, ARM_FEATURE_XSCALE))
+            if (arm_feature(env, ARM_FEATURE_XSCALE)) {
+                env->cp15.c1_xscaleauxcr = val;
                 break;
+            }
             goto bad_reg;
         case 2:
+            if (arm_feature(env, ARM_FEATURE_XSCALE))
+                goto bad_reg;
             env->cp15.c1_coproc = val;
             /* ??? Is this safe when called from within a TB?  */
             tb_flush(env);
@@ -835,6 +844,8 @@ uint32_t helper_get_cp15(CPUState *env, uint32_t insn)
         case 1: /* Cache Type.  */
             return env->cp15.c0_cachetype;
         case 2: /* TCM status.  */
+            if (arm_feature(env, ARM_FEATURE_XSCALE))
+                goto bad_reg;
             return 0;
         }
     case 1: /* System configuration.  */
@@ -845,9 +856,11 @@ uint32_t helper_get_cp15(CPUState *env, uint32_t insn)
             if (arm_feature(env, ARM_FEATURE_AUXCR))
                 return 1;
             if (arm_feature(env, ARM_FEATURE_XSCALE))
-                return 0;
+                return env->cp15.c1_xscaleauxcr;
             goto bad_reg;
         case 2: /* Coprocessor access register.  */
+            if (arm_feature(env, ARM_FEATURE_XSCALE))
+                goto bad_reg;
             return env->cp15.c1_coproc;
         default:
             goto bad_reg;

diff --git a/vl.c b/vl.c
index 4def8ab..22ded6b 100644 (file)
--- a/vl.c
+++ b/vl.c
@@ -5717,6 +5717,7 @@ void cpu_save(QEMUFile *f, void *opaque)
     qemu_put_be32(f, env->cp15.c0_cachetype);
     qemu_put_be32(f, env->cp15.c1_sys);
     qemu_put_be32(f, env->cp15.c1_coproc);
+    qemu_put_be32(f, env->cp15.c1_xscaleauxcr);
     qemu_put_be32(f, env->cp15.c2_base);
     qemu_put_be32(f, env->cp15.c2_data);
     qemu_put_be32(f, env->cp15.c2_insn);
@@ -5788,6 +5789,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
     env->cp15.c0_cachetype = qemu_get_be32(f);
     env->cp15.c1_sys = qemu_get_be32(f);
     env->cp15.c1_coproc = qemu_get_be32(f);
+    env->cp15.c1_xscaleauxcr = qemu_get_be32(f);
     env->cp15.c2_base = qemu_get_be32(f);
     env->cp15.c2_data = qemu_get_be32(f);
     env->cp15.c2_insn = qemu_get_be32(f);