mpc83xx: cosmetic: sbc8349.h checkpatch compliance
authorJoe Hershberger <joe.hershberger@ni.com>
Wed, 12 Oct 2011 04:57:25 +0000 (23:57 -0500)
committerKim Phillips <kim.phillips@freescale.com>
Thu, 3 Nov 2011 23:27:55 +0000 (18:27 -0500)
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
include/configs/sbc8349.h

index 7de90d5..6d38049 100644 (file)
@@ -71,7 +71,7 @@
 
 #define CONFIG_SYS_IMMR                0xE0000000
 
-#undef CONFIG_SYS_DRAM_TEST                            /* memory test, takes time */
+#undef CONFIG_SYS_DRAM_TEST            /* memory test, takes time */
 #define CONFIG_SYS_MEMTEST_START       0x00000000      /* memtest region */
 #define CONFIG_SYS_MEMTEST_END         0x00100000
 
@@ -81,7 +81,7 @@
 #undef CONFIG_DDR_ECC                  /* only for ECC DDR module */
 #undef CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
 #define CONFIG_SPD_EEPROM              /* use SPD EEPROM for DDR setup*/
-#define CONFIG_SYS_83XX_DDR_USES_CS0           /* WRS; Fsl board uses CS2/CS3 */
+#define CONFIG_SYS_83XX_DDR_USES_CS0   /* WRS; Fsl board uses CS2/CS3 */
 
 /*
  * 32-bit data path mode.
@@ -95,7 +95,7 @@
  */
 #undef CONFIG_DDR_32BIT
 
-#define CONFIG_SYS_DDR_BASE            0x00000000      /* DDR is system memory*/
+#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory*/
 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN | \
  * NB: manual DDR setup untested on sbc834x
  */
 #define CONFIG_SYS_DDR_SIZE            256             /* MB */
-#define CONFIG_SYS_DDR_CONFIG          (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+#define CONFIG_SYS_DDR_CONFIG          (CSCONFIG_EN \
+                                       | CSCONFIG_ROW_BIT_13 \
+                                       | CSCONFIG_COL_BIT_10)
 #define CONFIG_SYS_DDR_TIMING_1        0x36332321
 #define CONFIG_SYS_DDR_TIMING_2        0x00000800      /* P9-45,may need tuning */
-#define CONFIG_SYS_DDR_CONTROL         0xc2000000      /* unbuffered,no DYN_PWR */
+#define CONFIG_SYS_DDR_CONTROL 0xc2000000      /* unbuffered,no DYN_PWR */
 #define CONFIG_SYS_DDR_INTERVAL        0x04060100      /* autocharge,no open page */
 
 #if defined(CONFIG_DDR_32BIT)
 /* set burst length to 8 for 32-bit data path */
-#define CONFIG_SYS_DDR_MODE            0x00000023      /* DLL,normal,seq,4/2.5, 8 burst len */
+                               /* DLL,normal,seq,4/2.5, 8 burst len */
+#define CONFIG_SYS_DDR_MODE    0x00000023
 #else
 /* the default burst length is 4 - for 64-bit data path */
-#define CONFIG_SYS_DDR_MODE            0x00000022      /* DLL,normal,seq,4/2.5, 4 burst len */
+                               /* DLL,normal,seq,4/2.5, 4 burst len */
+#define CONFIG_SYS_DDR_MODE    0x00000022
 #endif
 #endif
 
  * SDRAM on the Local Bus
  */
 #define CONFIG_SYS_LBC_SDRAM_BASE      0x10000000      /* Localbus SDRAM */
-#define CONFIG_SYS_LBC_SDRAM_SIZE      128             /* LBC SDRAM is 128MB */
+#define CONFIG_SYS_LBC_SDRAM_SIZE      128     /* LBC SDRAM is 128MB */
 
 /*
  * FLASH on the Local Bus
  */
-#define CONFIG_SYS_FLASH_CFI                           /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER                        /* use the CFI driver */
+#define CONFIG_SYS_FLASH_CFI           /* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER                /* use the CFI driver */
 #define CONFIG_SYS_FLASH_BASE          0xFF800000      /* start of FLASH   */
 #define CONFIG_SYS_FLASH_SIZE          8               /* flash size in MB */
 /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 
-#define CONFIG_SYS_BR0_PRELIM          (CONFIG_SYS_FLASH_BASE |        /* flash Base address */ \
-                               (2 << BR_PS_SHIFT) |    /* 16 bit port size */   \
-                               BR_V)                   /* valid */
+#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
+                               | (2 << BR_PS_SHIFT)    /* 16 bit port */ \
+                               | BR_V)                 /* valid */
 
 #define CONFIG_SYS_OR0_PRELIM          0xFF806FF7      /* 8 MB flash size */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM    CONFIG_SYS_FLASH_BASE   /* window base at flash base */
+                                       /* window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM    CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_LBLAWAR0_PRELIM     0x80000016      /* 8 MB window size */
 
-#define CONFIG_SYS_MAX_FLASH_BANKS     1               /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT      64              /* sectors per device */
+#define CONFIG_SYS_MAX_FLASH_BANKS     1       /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT      64      /* sectors per device */
 
 #undef CONFIG_SYS_FLASH_CHECKSUM
 #define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
 #endif
 
 #define CONFIG_SYS_INIT_RAM_LOCK       1
-#define CONFIG_SYS_INIT_RAM_ADDR       0xFD000000              /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE       0x1000                  /* Size of used area in RAM*/
+                                       /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_ADDR       0xFD000000
+                                       /* Size of used area in RAM*/
+#define CONFIG_SYS_INIT_RAM_SIZE       0x1000
 
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET     \
+                       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CONFIG_SYS_MONITOR_LEN         (256 * 1024)            /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN          (128 * 1024)            /* Reserved for malloc */
+#define CONFIG_SYS_MONITOR_LEN (256 * 1024)    /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN  (128 * 1024)    /* Reserved for malloc */
 
 /*
  * Local Bus LCRR and LBCR regs
  * FIXME: the top 17 bits of BR2.
  */
 
-#define CONFIG_SYS_BR2_PRELIM          0xF0001861 /* Port-size=32bit, MSEL=SDRAM */
+                                       /* Port-size=32bit, MSEL=SDRAM */
+#define CONFIG_SYS_BR2_PRELIM          0xF0001861
 #define CONFIG_SYS_LBLAWBAR2_PRELIM    0xF0000000
 #define CONFIG_SYS_LBLAWAR2_PRELIM     0x80000019 /* 64M */
 
 
 #define CONFIG_SYS_OR2_PRELIM  0xFC006901
 
-#define CONFIG_SYS_LBC_LSRT    0x32000000    /* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_MRTPR   0x20000000    /* LB refresh timer prescal, 266MHz/32 */
+                               /* LB sdram refresh timer, about 6us */
+#define CONFIG_SYS_LBC_LSRT    0x32000000
+                               /* LB refresh timer prescal, 266MHz/32 */
+#define CONFIG_SYS_LBC_MRTPR   0x20000000
 
-#define CONFIG_SYS_LBC_LSDMR_COMMON    ( LSDMR_RFEN            \
-                               | LSDMR_BSMA1516        \
-                               | LSDMR_RFCR8           \
-                               | LSDMR_PRETOACT6       \
-                               | LSDMR_ACTTORW3        \
-                               | LSDMR_BL8             \
-                               | LSDMR_WRC3            \
-                               | LSDMR_CL3             \
-                               )
+#define CONFIG_SYS_LBC_LSDMR_COMMON    (LSDMR_RFEN \
+                                       | LSDMR_BSMA1516 \
+                                       | LSDMR_RFCR8 \
+                                       | LSDMR_PRETOACT6 \
+                                       | LSDMR_ACTTORW3 \
+                                       | LSDMR_BL8 \
+                                       | LSDMR_WRC3 \
+                                       | LSDMR_CL3)
 
 /*
  * SDRAM Controller configuration sequence.
 #define CONFIG_SYS_NS16550_CLK         get_bus_freq(0)
 
 #define CONFIG_SYS_BAUDRATE_TABLE  \
-       {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+               {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 
 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 #define CONFIG_AUTO_COMPLETE           /* add autocompletion support   */
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
-#ifdef  CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 #endif
 
 #define CONFIG_HARD_I2C                        /* I2C with hardware support*/
 #undef CONFIG_SOFT_I2C                 /* I2C bit-banged */
 #define CONFIG_FSL_I2C
-#define CONFIG_SYS_I2C_SPEED           400000  /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE           0x7F
+#define CONFIG_SYS_I2C_SPEED   400000  /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE   0x7F
 #define CONFIG_SYS_I2C_NOPROBES        {0x69}  /* Don't probe these addrs */
-#define CONFIG_SYS_I2C1_OFFSET         0x3000
-#define CONFIG_SYS_I2C2_OFFSET         0x3100
-#define CONFIG_SYS_I2C_OFFSET          CONFIG_SYS_I2C2_OFFSET
+#define CONFIG_SYS_I2C1_OFFSET 0x3000
+#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C_OFFSET  CONFIG_SYS_I2C2_OFFSET
 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */
 
 /* TSEC */
 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC1       (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+#define CONFIG_SYS_TSEC2       (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 
 /*
  * General PCI
 #define CONFIG_SYS_PCI1_MMIO_BASE      0x90000000
 #define CONFIG_SYS_PCI1_MMIO_PHYS      CONFIG_SYS_PCI1_MMIO_BASE
 #define CONFIG_SYS_PCI1_MMIO_SIZE      0x10000000      /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE        0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS        0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE        0x00100000      /* 1M */
+#define CONFIG_SYS_PCI1_IO_BASE                0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS                0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE                0x00100000      /* 1M */
 
 #define CONFIG_SYS_PCI2_MEM_BASE       0xA0000000
 #define CONFIG_SYS_PCI2_MEM_PHYS       CONFIG_SYS_PCI2_MEM_BASE
 #define CONFIG_SYS_PCI2_MMIO_BASE      0xB0000000
 #define CONFIG_SYS_PCI2_MMIO_PHYS      CONFIG_SYS_PCI2_MMIO_BASE
 #define CONFIG_SYS_PCI2_MMIO_SIZE      0x10000000      /* 256M */
-#define CONFIG_SYS_PCI2_IO_BASE        0x00000000
-#define CONFIG_SYS_PCI2_IO_PHYS        0xE2100000
-#define CONFIG_SYS_PCI2_IO_SIZE        0x00100000      /* 1M */
+#define CONFIG_SYS_PCI2_IO_BASE                0x00000000
+#define CONFIG_SYS_PCI2_IO_PHYS                0xE2100000
+#define CONFIG_SYS_PCI2_IO_SIZE                0x00100000      /* 1M */
 
 #if defined(CONFIG_PCI)
 
 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
 
 #else
-       #define CONFIG_SYS_NO_FLASH             1       /* Flash is not usable now */
+       #define CONFIG_SYS_NO_FLASH     1       /* Flash is not usable now */
        #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
        #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
        #define CONFIG_ENV_SIZE         0x2000
 #define CONFIG_SYS_PROMPT      "=> "           /* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
-       #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
+       #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 #else
-       #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
+       #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 #endif
 
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS     16              /* max number of command args */
-#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ          1000            /* decrementer freq: 1ms ticks */
+                               /* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS     16      /* max number of command args */
+                               /* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ          1000    /* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 256 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ   (256 << 20)     /* Initial Memory map for Linux*/
+                               /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTMAPSZ   (256 << 20)
 
 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 
        HRCWH_SW_WATCHDOG_DISABLE |\
        HRCWH_ROM_LOC_LOCAL_16BIT |\
        HRCWH_TSEC1M_IN_GMII |\
-       HRCWH_TSEC2M_IN_GMII )
+       HRCWH_TSEC2M_IN_GMII)
 #else
 #define CONFIG_SYS_HRCW_HIGH (\
        HRCWH_PCI_HOST |\
        HRCWH_SW_WATCHDOG_DISABLE |\
        HRCWH_ROM_LOC_LOCAL_16BIT |\
        HRCWH_TSEC1M_IN_GMII |\
-       HRCWH_TSEC2M_IN_GMII )
+       HRCWH_TSEC2M_IN_GMII)
 #endif
 
 /* System IO Config */
 #define CONFIG_SYS_SICRL SICRL_LDP_A
 
 #define CONFIG_SYS_HID0_INIT   0x000000000
-#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK \
-                                HID0_ENABLE_INSTRUCTION_CACHE)
+#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK \
+                               | HID0_ENABLE_INSTRUCTION_CACHE)
 
-/* #define CONFIG_SYS_HID0_FINAL               (\
+/* #define CONFIG_SYS_HID0_FINAL       (\
        HID0_ENABLE_INSTRUCTION_CACHE |\
        HID0_ENABLE_M_BIT |\
-       HID0_ENABLE_ADDRESS_BROADCAST ) */
+       HID0_ENABLE_ADDRESS_BROADCAST) */
 
 
 #define CONFIG_SYS_HID2 HID2_HBE
 #define CONFIG_HIGH_BATS       1       /* High BATs supported */
 
 /* DDR @ 0x00000000 */
-#define CONFIG_SYS_IBAT0L      (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U      (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L      (CONFIG_SYS_SDRAM_BASE \
+                               | BATL_PP_10 \
+                               | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U      (CONFIG_SYS_SDRAM_BASE \
+                               | BATU_BL_256M \
+                               | BATU_VS \
+                               | BATU_VP)
 
 /* PCI @ 0x80000000 */
 #ifdef CONFIG_PCI
-#define CONFIG_SYS_IBAT1L      (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U      (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT2L      (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U      (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L      (CONFIG_SYS_PCI1_MEM_BASE \
+                               | BATL_PP_10 \
+                               | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT1U      (CONFIG_SYS_PCI1_MEM_BASE \
+                               | BATU_BL_256M \
+                               | BATU_VS \
+                               | BATU_VP)
+#define CONFIG_SYS_IBAT2L      (CONFIG_SYS_PCI1_MMIO_BASE \
+                               | BATL_PP_10 \
+                               | BATL_CACHEINHIBIT \
+                               | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U      (CONFIG_SYS_PCI1_MMIO_BASE \
+                               | BATU_BL_256M \
+                               | BATU_VS \
+                               | BATU_VP)
 #else
 #define CONFIG_SYS_IBAT1L      (0)
 #define CONFIG_SYS_IBAT1U      (0)
 #endif
 
 #ifdef CONFIG_MPC83XX_PCI2
-#define CONFIG_SYS_IBAT3L      (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U      (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT4L      (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT4U      (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L      (CONFIG_SYS_PCI2_MEM_BASE \
+                               | BATL_PP_10 \
+                               | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT3U      (CONFIG_SYS_PCI2_MEM_BASE \
+                               | BATU_BL_256M \
+                               | BATU_VS \
+                               | BATU_VP)
+#define CONFIG_SYS_IBAT4L      (CONFIG_SYS_PCI2_MMIO_BASE \
+                               | BATL_PP_10 \
+                               | BATL_CACHEINHIBIT \
+                               | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT4U      (CONFIG_SYS_PCI2_MMIO_BASE \
+                               | BATU_BL_256M \
+                               | BATU_VS \
+                               | BATU_VP)
 #else
 #define CONFIG_SYS_IBAT3L      (0)
 #define CONFIG_SYS_IBAT3U      (0)
 #endif
 
 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
-#define CONFIG_SYS_IBAT5L      (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U      (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT5L      (CONFIG_SYS_IMMR \
+                               | BATL_PP_10 \
+                               | BATL_CACHEINHIBIT \
+                               | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U      (CONFIG_SYS_IMMR \
+                               | BATU_BL_256M \
+                               | BATU_VS \
+                               | BATU_VP)
 
 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L      (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \
-                                BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6L      (0xF0000000 \
+                               | BATL_PP_10 \
+                               | BATL_MEMCOHERENCE \
+                               | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT6U      (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
 #define CONFIG_SYS_IBAT7L      (0)
 #define CONFIG_ROOTPATH                "/tftpboot/rootfs"
 #define CONFIG_BOOTFILE                "uImage"
 
-#define CONFIG_LOADADDR                800000  /* default location for tftp and bootm */
+                               /* default location for tftp and bootm */
+#define CONFIG_LOADADDR                800000
 
 #define CONFIG_BOOTDELAY       6       /* -1 disables auto-boot */
-#undef  CONFIG_BOOTARGS                        /* the boot command will set bootargs */
+#undef  CONFIG_BOOTARGS                /* the boot command will set bootargs */
 
 #define CONFIG_BAUDRATE         115200
 
                "bootm\0"                                               \
        "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0"               \
        "update=protect off ff800000 ff83ffff; "                        \
-               "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0"     \
+               "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \
        "upd=run load update\0"                                         \
        "fdtaddr=780000\0"                                              \
        "fdtfile=sbc8349.dtb\0"                                         \
        ""
 
-#define CONFIG_NFSBOOTCOMMAND                                          \
-   "setenv bootargs root=/dev/nfs rw "                                  \
-      "nfsroot=$serverip:$rootpath "                                    \
-      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-      "console=$consoledev,$baudrate $othbootargs;"                     \
-   "tftp $loadaddr $bootfile;"                                          \
-   "tftp $fdtaddr $fdtfile;"                                           \
-   "bootm $loadaddr - $fdtaddr"
+#define CONFIG_NFSBOOTCOMMAND                                          \
+       "setenv bootargs root=/dev/nfs rw "                             \
+               "nfsroot=$serverip:$rootpath "                          \
+               "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
+                                                       "$netdev:off "  \
+               "console=$consoledev,$baudrate $othbootargs;"           \
+       "tftp $loadaddr $bootfile;"                                     \
+       "tftp $fdtaddr $fdtfile;"                                       \
+       "bootm $loadaddr - $fdtaddr"
 
 #define CONFIG_RAMBOOTCOMMAND                                          \
-   "setenv bootargs root=/dev/ram rw "                                  \
-      "console=$consoledev,$baudrate $othbootargs;"                     \
-   "tftp $ramdiskaddr $ramdiskfile;"                                    \
-   "tftp $loadaddr $bootfile;"                                          \
-   "tftp $fdtaddr $fdtfile;"                                           \
-   "bootm $loadaddr $ramdiskaddr $fdtaddr"
+       "setenv bootargs root=/dev/ram rw "                             \
+               "console=$consoledev,$baudrate $othbootargs;"           \
+       "tftp $ramdiskaddr $ramdiskfile;"                               \
+       "tftp $loadaddr $bootfile;"                                     \
+       "tftp $fdtaddr $fdtfile;"                                       \
+       "bootm $loadaddr $ramdiskaddr $fdtaddr"
 
 #define CONFIG_BOOTCOMMAND     "run flash_self"