[RISCV][llvm-mca] Add mca tests for riscv lmul instruments

Add llvm-mca tests for RISCV LMUL instruments to show that llvm-mca RISCV LMUL
instruments work.

This commit was previously reverted in 847789d45712. It is now being
recommitted since the memory leak has been fixed in 4d2a1d7dd8f4.

Differential Revision: https://reviews.llvm.org/D149496

diff --git a/llvm/test/tools/llvm-mca/RISCV/different-instruments.s b/llvm/test/tools/llvm-mca/RISCV/different-instruments.s
new file mode 100644 (file)
index 0000000..ced206a
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/different-instruments.s
@@ -0,0 +1,76 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, a0, e8, m1, tu, mu
+# LLVM-MCA-RISCV-LMUL M1
+vadd.vv v12, v12, v12
+vsetvli zero, a0, e8, m8, tu, mu
+# LLVM-MCA-RISCV-LMUL M8
+vadd.vv v12, v12, v12
+
+# CHECK:      Iterations:        1
+# CHECK-NEXT: Instructions:      4
+# CHECK-NEXT: Total Cycles:      12
+# CHECK-NEXT: Total uOps:        4
+
+# CHECK:      Dispatch Width:    2
+# CHECK-NEXT: uOps Per Cycle:    0.33
+# CHECK-NEXT: IPC:               0.33
+# CHECK-NEXT: Block RThroughput: 18.0
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli        zero, a0, e8, m1, tu, mu
+# CHECK-NEXT:  1      4     16.00                       vadd.vv        v12, v12, v12
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli        zero, a0, e8, m8, tu, mu
+# CHECK-NEXT:  1      4     16.00                       vadd.vv        v12, v12, v12
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - SiFive7FDiv
+# CHECK-NEXT: [1]   - SiFive7IDiv
+# CHECK-NEXT: [2]   - SiFive7PipeA
+# CHECK-NEXT: [3]   - SiFive7PipeB
+# CHECK-NEXT: [4]   - SiFive7PipeV
+# CHECK-NEXT: [5]   - SiFive7VA
+# CHECK-NEXT: [6]   - SiFive7VL
+# CHECK-NEXT: [7]   - SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
+# CHECK-NEXT:  -      -     2.00    -     18.00  18.00   -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli  zero, a0, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00   2.00    -      -     vadd.vv  v12, v12, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli  zero, a0, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     16.00  16.00   -      -     vadd.vv  v12, v12, v12
+
+# CHECK:      Timeline view:
+# CHECK-NEXT:                     01
+# CHECK-NEXT: Index     0123456789
+
+# CHECK:      [0,0]     DeeE .    ..   vsetvli zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: [0,1]     .  DeeeE  ..   vadd.vv v12, v12, v12
+# CHECK-NEXT: [0,2]     .   DeeE  ..   vsetvli zero, a0, e8, m8, tu, mu
+# CHECK-NEXT: [0,3]     .    . DeeeE   vadd.vv v12, v12, v12
+
+# CHECK:      Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK:            [0]    [1]    [2]    [3]
+# CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli     zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vadd.vv     v12, v12, v12
+# CHECK-NEXT: 2.     1     0.0    0.0    0.0       vsetvli     zero, a0, e8, m8, tu, mu
+# CHECK-NEXT: 3.     1     0.0    0.0    0.0       vadd.vv     v12, v12, v12
+# CHECK-NEXT:        1     0.0    0.0    0.0       <total>

diff --git a/llvm/test/tools/llvm-mca/RISCV/disable-im.s b/llvm/test/tools/llvm-mca/RISCV/disable-im.s
new file mode 100644 (file)
index 0000000..fc969bf
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/disable-im.s
@@ -0,0 +1,87 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 -disable-im < %s | FileCheck %s
+
+vsetvli zero, a0, e8, m2, tu, mu
+# LLVM-MCA-RISCV-LMUL M2
+vadd.vv v12, v12, v12
+vsetvli zero, a0, e8, m1, tu, mu
+# LLVM-MCA-RISCV-LMUL M1
+vadd.vv v12, v12, v12
+vsetvli zero, a0, e8, m8, tu, mu
+# LLVM-MCA-RISCV-LMUL M8
+vadd.vv v12, v12, v12
+
+# CHECK:      Iterations:        1
+# CHECK-NEXT: Instructions:      6
+# CHECK-NEXT: Total Cycles:      40
+# CHECK-NEXT: Total uOps:        6
+
+# CHECK:      Dispatch Width:    2
+# CHECK-NEXT: uOps Per Cycle:    0.15
+# CHECK-NEXT: IPC:               0.15
+# CHECK-NEXT: Block RThroughput: 48.0
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli        zero, a0, e8, m2, tu, mu
+# CHECK-NEXT:  1      4     16.00                       vadd.vv        v12, v12, v12
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli        zero, a0, e8, m1, tu, mu
+# CHECK-NEXT:  1      4     16.00                       vadd.vv        v12, v12, v12
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli        zero, a0, e8, m8, tu, mu
+# CHECK-NEXT:  1      4     16.00                       vadd.vv        v12, v12, v12
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - SiFive7FDiv
+# CHECK-NEXT: [1]   - SiFive7IDiv
+# CHECK-NEXT: [2]   - SiFive7PipeA
+# CHECK-NEXT: [3]   - SiFive7PipeB
+# CHECK-NEXT: [4]   - SiFive7PipeV
+# CHECK-NEXT: [5]   - SiFive7VA
+# CHECK-NEXT: [6]   - SiFive7VL
+# CHECK-NEXT: [7]   - SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
+# CHECK-NEXT:  -      -     3.00    -     48.00  48.00   -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli  zero, a0, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     16.00  16.00   -      -     vadd.vv  v12, v12, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli  zero, a0, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     16.00  16.00   -      -     vadd.vv  v12, v12, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli  zero, a0, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     16.00  16.00   -      -     vadd.vv  v12, v12, v12
+
+# CHECK:      Timeline view:
+# CHECK-NEXT:                     0123456789          0123456789
+# CHECK-NEXT: Index     0123456789          0123456789
+
+# CHECK:      [0,0]     DeeE .    .    .    .    .    .    .   .   vsetvli     zero, a0, e8, m2, tu, mu
+# CHECK-NEXT: [0,1]     .  DeeeE  .    .    .    .    .    .   .   vadd.vv     v12, v12, v12
+# CHECK-NEXT: [0,2]     .   DeeE  .    .    .    .    .    .   .   vsetvli     zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: [0,3]     .    .    .    .   DeeeE .    .    .   .   vadd.vv     v12, v12, v12
+# CHECK-NEXT: [0,4]     .    .    .    .    DeeE .    .    .   .   vsetvli     zero, a0, e8, m8, tu, mu
+# CHECK-NEXT: [0,5]     .    .    .    .    .    .    .    DeeeE   vadd.vv     v12, v12, v12
+
+# CHECK:      Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK:            [0]    [1]    [2]    [3]
+# CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli     zero, a0, e8, m2, tu, mu
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vadd.vv     v12, v12, v12
+# CHECK-NEXT: 2.     1     0.0    0.0    0.0       vsetvli     zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: 3.     1     0.0    0.0    0.0       vadd.vv     v12, v12, v12
+# CHECK-NEXT: 4.     1     0.0    0.0    0.0       vsetvli     zero, a0, e8, m8, tu, mu
+# CHECK-NEXT: 5.     1     0.0    0.0    0.0       vadd.vv     v12, v12, v12
+# CHECK-NEXT:        1     0.0    0.0    0.0       <total>

diff --git a/llvm/test/tools/llvm-mca/RISCV/instrument-at-start.s b/llvm/test/tools/llvm-mca/RISCV/instrument-at-start.s
new file mode 100644 (file)
index 0000000..fd33e2a
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/instrument-at-start.s
@@ -0,0 +1,64 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, a0, e8, m1, tu, mu
+# LLVM-MCA-RISCV-LMUL M1
+vadd.vv v12, v12, v12
+
+# CHECK:      Iterations:        1
+# CHECK-NEXT: Instructions:      2
+# CHECK-NEXT: Total Cycles:      8
+# CHECK-NEXT: Total uOps:        2
+
+# CHECK:      Dispatch Width:    2
+# CHECK-NEXT: uOps Per Cycle:    0.25
+# CHECK-NEXT: IPC:               0.25
+# CHECK-NEXT: Block RThroughput: 2.0
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli        zero, a0, e8, m1, tu, mu
+# CHECK-NEXT:  1      4     16.00                       vadd.vv        v12, v12, v12
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - SiFive7FDiv
+# CHECK-NEXT: [1]   - SiFive7IDiv
+# CHECK-NEXT: [2]   - SiFive7PipeA
+# CHECK-NEXT: [3]   - SiFive7PipeB
+# CHECK-NEXT: [4]   - SiFive7PipeV
+# CHECK-NEXT: [5]   - SiFive7VA
+# CHECK-NEXT: [6]   - SiFive7VL
+# CHECK-NEXT: [7]   - SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
+# CHECK-NEXT:  -      -     1.00    -     2.00   2.00    -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli  zero, a0, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00   2.00    -      -     vadd.vv  v12, v12, v12
+
+# CHECK:      Timeline view:
+# CHECK-NEXT: Index     01234567
+
+# CHECK:      [0,0]     DeeE . .   vsetvli     zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: [0,1]     .  DeeeE   vadd.vv     v12, v12, v12
+
+# CHECK:      Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK:            [0]    [1]    [2]    [3]
+# CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli     zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vadd.vv     v12, v12, v12
+# CHECK-NEXT:        1     0.0    0.0    0.0       <total>

diff --git a/llvm/test/tools/llvm-mca/RISCV/instrument-in-middle.s b/llvm/test/tools/llvm-mca/RISCV/instrument-in-middle.s
new file mode 100644 (file)
index 0000000..90fe5c6
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/instrument-in-middle.s
@@ -0,0 +1,70 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
+
+vadd.vv v12, v12, v12
+vsetvli zero, a0, e8, m8, tu, mu
+# LLVM-MCA-RISCV-LMUL MF8
+vadd.vv v12, v12, v12
+
+# CHECK:      Iterations:        1
+# CHECK-NEXT: Instructions:      3
+# CHECK-NEXT: Total Cycles:      21
+# CHECK-NEXT: Total uOps:        3
+
+# CHECK:      Dispatch Width:    2
+# CHECK-NEXT: uOps Per Cycle:    0.14
+# CHECK-NEXT: IPC:               0.14
+# CHECK-NEXT: Block RThroughput: 17.0
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      4     16.00                       vadd.vv        v12, v12, v12
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli        zero, a0, e8, m8, tu, mu
+# CHECK-NEXT:  1      4     16.00                       vadd.vv        v12, v12, v12
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - SiFive7FDiv
+# CHECK-NEXT: [1]   - SiFive7IDiv
+# CHECK-NEXT: [2]   - SiFive7PipeA
+# CHECK-NEXT: [3]   - SiFive7PipeB
+# CHECK-NEXT: [4]   - SiFive7PipeV
+# CHECK-NEXT: [5]   - SiFive7VA
+# CHECK-NEXT: [6]   - SiFive7VL
+# CHECK-NEXT: [7]   - SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
+# CHECK-NEXT:  -      -     1.00    -     17.00  17.00   -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
+# CHECK-NEXT:  -      -      -      -     16.00  16.00   -      -     vadd.vv  v12, v12, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli  zero, a0, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     1.00   1.00    -      -     vadd.vv  v12, v12, v12
+
+# CHECK:      Timeline view:
+# CHECK-NEXT:                     0123456789
+# CHECK-NEXT: Index     0123456789          0
+
+# CHECK:      [0,0]     DeeeE.    .    .    .   vadd.vv        v12, v12, v12
+# CHECK-NEXT: [0,1]     .DeeE.    .    .    .   vsetvli        zero, a0, e8, m8, tu, mu
+# CHECK-NEXT: [0,2]     .    .    .    .DeeeE   vadd.vv        v12, v12, v12
+
+# CHECK:      Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK:            [0]    [1]    [2]    [3]
+# CHECK-NEXT: 0.     1     0.0    0.0    0.0       vadd.vv     v12, v12, v12
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vsetvli     zero, a0, e8, m8, tu, mu
+# CHECK-NEXT: 2.     1     0.0    0.0    0.0       vadd.vv     v12, v12, v12
+# CHECK-NEXT:        1     0.0    0.0    0.0       <total>

diff --git a/llvm/test/tools/llvm-mca/RISCV/instrument-in-region.s b/llvm/test/tools/llvm-mca/RISCV/instrument-in-region.s
new file mode 100644 (file)
index 0000000..f33ae27
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/instrument-in-region.s
@@ -0,0 +1,68 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
+
+# LLVM-MCA-BEGIN foo
+vsetvli zero, a0, e8, m1, tu, mu
+# LLVM-MCA-RISCV-LMUL M1
+vadd.vv v12, v12, v12
+# LLVM-MCA-END foo
+
+# CHECK:      [0] Code Region - foo
+
+# CHECK:      Iterations:        1
+# CHECK-NEXT: Instructions:      2
+# CHECK-NEXT: Total Cycles:      8
+# CHECK-NEXT: Total uOps:        2
+
+# CHECK:      Dispatch Width:    2
+# CHECK-NEXT: uOps Per Cycle:    0.25
+# CHECK-NEXT: IPC:               0.25
+# CHECK-NEXT: Block RThroughput: 2.0
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli        zero, a0, e8, m1, tu, mu
+# CHECK-NEXT:  1      4     16.00                       vadd.vv        v12, v12, v12
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - SiFive7FDiv
+# CHECK-NEXT: [1]   - SiFive7IDiv
+# CHECK-NEXT: [2]   - SiFive7PipeA
+# CHECK-NEXT: [3]   - SiFive7PipeB
+# CHECK-NEXT: [4]   - SiFive7PipeV
+# CHECK-NEXT: [5]   - SiFive7VA
+# CHECK-NEXT: [6]   - SiFive7VL
+# CHECK-NEXT: [7]   - SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
+# CHECK-NEXT:  -      -     1.00    -     2.00   2.00    -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli  zero, a0, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00   2.00    -      -     vadd.vv  v12, v12, v12
+
+# CHECK:      Timeline view:
+# CHECK-NEXT: Index     01234567
+
+# CHECK:      [0,0]     DeeE . .   vsetvli     zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: [0,1]     .  DeeeE   vadd.vv     v12, v12, v12
+
+# CHECK:      Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK:            [0]    [1]    [2]    [3]
+# CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli     zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vadd.vv     v12, v12, v12
+# CHECK-NEXT:        1     0.0    0.0    0.0       <total>

diff --git a/llvm/test/tools/llvm-mca/RISCV/instrument-straddles-region.s b/llvm/test/tools/llvm-mca/RISCV/instrument-straddles-region.s
new file mode 100644 (file)
index 0000000..c2187a3
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/instrument-straddles-region.s
@@ -0,0 +1,69 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
+
+# LLVM-MCA-BEGIN foo
+vsetvli zero, a0, e8, m1, tu, mu
+# LLVM-MCA-RISCV-LMUL M1
+vadd.vv v12, v12, v12
+# LLVM-MCA-END foo
+vadd.vv v12, v12, v12
+
+# CHECK:      [0] Code Region - foo
+
+# CHECK:      Iterations:        1
+# CHECK-NEXT: Instructions:      2
+# CHECK-NEXT: Total Cycles:      8
+# CHECK-NEXT: Total uOps:        2
+
+# CHECK:      Dispatch Width:    2
+# CHECK-NEXT: uOps Per Cycle:    0.25
+# CHECK-NEXT: IPC:               0.25
+# CHECK-NEXT: Block RThroughput: 2.0
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli        zero, a0, e8, m1, tu, mu
+# CHECK-NEXT:  1      4     16.00                       vadd.vv        v12, v12, v12
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - SiFive7FDiv
+# CHECK-NEXT: [1]   - SiFive7IDiv
+# CHECK-NEXT: [2]   - SiFive7PipeA
+# CHECK-NEXT: [3]   - SiFive7PipeB
+# CHECK-NEXT: [4]   - SiFive7PipeV
+# CHECK-NEXT: [5]   - SiFive7VA
+# CHECK-NEXT: [6]   - SiFive7VL
+# CHECK-NEXT: [7]   - SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
+# CHECK-NEXT:  -      -     1.00    -     2.00   2.00    -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli  zero, a0, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00   2.00    -      -     vadd.vv  v12, v12, v12
+
+# CHECK:      Timeline view:
+# CHECK-NEXT: Index     01234567
+
+# CHECK:      [0,0]     DeeE . .   vsetvli     zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: [0,1]     .  DeeeE   vadd.vv     v12, v12, v12
+
+# CHECK:      Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK:            [0]    [1]    [2]    [3]
+# CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli     zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vadd.vv     v12, v12, v12
+# CHECK-NEXT:        1     0.0    0.0    0.0       <total>

diff --git a/llvm/test/tools/llvm-mca/RISCV/lit.local.cfg b/llvm/test/tools/llvm-mca/RISCV/lit.local.cfg
new file mode 100644 (file)
index 0000000..c638201
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'RISCV' in config.root.targets:
+    config.unsupported = True

diff --git a/llvm/test/tools/llvm-mca/RISCV/multiple-same-instruments.s b/llvm/test/tools/llvm-mca/RISCV/multiple-same-instruments.s
new file mode 100644 (file)
index 0000000..585908e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/multiple-same-instruments.s
@@ -0,0 +1,97 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, a0, e8, m1, tu, mu
+# LLVM-MCA-RISCV-LMUL M1
+vadd.vv v12, v12, v12
+vsetvli zero, a0, e8, m1, tu, mu
+# LLVM-MCA-RISCV-LMUL M1
+vadd.vv v12, v12, v12
+vsub.vv v12, v12, v12
+vsetvli zero, a0, e8, m2, tu, mu
+# LLVM-MCA-RISCV-LMUL M4
+vadd.vv v12, v12, v12
+vsub.vv v12, v12, v12
+
+# CHECK:      Iterations:        1
+# CHECK-NEXT: Instructions:      8
+# CHECK-NEXT: Total Cycles:      28
+# CHECK-NEXT: Total uOps:        8
+
+# CHECK:      Dispatch Width:    2
+# CHECK-NEXT: uOps Per Cycle:    0.29
+# CHECK-NEXT: IPC:               0.29
+# CHECK-NEXT: Block RThroughput: 22.0
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli        zero, a0, e8, m1, tu, mu
+# CHECK-NEXT:  1      4     16.00                       vadd.vv        v12, v12, v12
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli        zero, a0, e8, m1, tu, mu
+# CHECK-NEXT:  1      4     16.00                       vadd.vv        v12, v12, v12
+# CHECK-NEXT:  1      4     16.00                       vsub.vv        v12, v12, v12
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli        zero, a0, e8, m2, tu, mu
+# CHECK-NEXT:  1      4     16.00                       vadd.vv        v12, v12, v12
+# CHECK-NEXT:  1      4     16.00                       vsub.vv        v12, v12, v12
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - SiFive7FDiv
+# CHECK-NEXT: [1]   - SiFive7IDiv
+# CHECK-NEXT: [2]   - SiFive7PipeA
+# CHECK-NEXT: [3]   - SiFive7PipeB
+# CHECK-NEXT: [4]   - SiFive7PipeV
+# CHECK-NEXT: [5]   - SiFive7VA
+# CHECK-NEXT: [6]   - SiFive7VL
+# CHECK-NEXT: [7]   - SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
+# CHECK-NEXT:  -      -     3.00    -     22.00  22.00   -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli  zero, a0, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00   2.00    -      -     vadd.vv  v12, v12, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli  zero, a0, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     2.00   2.00    -      -     vadd.vv  v12, v12, v12
+# CHECK-NEXT:  -      -      -      -     2.00   2.00    -      -     vsub.vv  v12, v12, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli  zero, a0, e8, m2, tu, mu
+# CHECK-NEXT:  -      -      -      -     8.00   8.00    -      -     vadd.vv  v12, v12, v12
+# CHECK-NEXT:  -      -      -      -     8.00   8.00    -      -     vsub.vv  v12, v12, v12
+
+# CHECK:      Timeline view:
+# CHECK-NEXT:                     0123456789
+# CHECK-NEXT: Index     0123456789          01234567
+
+# CHECK:      [0,0]     DeeE .    .    .    .    . .   vsetvli zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: [0,1]     .  DeeeE  .    .    .    . .   vadd.vv v12, v12, v12
+# CHECK-NEXT: [0,2]     .   DeeE  .    .    .    . .   vsetvli zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: [0,3]     .    . DeeeE   .    .    . .   vadd.vv v12, v12, v12
+# CHECK-NEXT: [0,4]     .    .    .DeeeE    .    . .   vsub.vv v12, v12, v12
+# CHECK-NEXT: [0,5]     .    .    . DeeE    .    . .   vsetvli zero, a0, e8, m2, tu, mu
+# CHECK-NEXT: [0,6]     .    .    .    DeeeE.    . .   vadd.vv v12, v12, v12
+# CHECK-NEXT: [0,7]     .    .    .    .    .  DeeeE   vsub.vv v12, v12, v12
+
+# CHECK:      Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK:            [0]    [1]    [2]    [3]
+# CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli     zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vadd.vv     v12, v12, v12
+# CHECK-NEXT: 2.     1     0.0    0.0    0.0       vsetvli     zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: 3.     1     0.0    0.0    0.0       vadd.vv     v12, v12, v12
+# CHECK-NEXT: 4.     1     0.0    0.0    0.0       vsub.vv     v12, v12, v12
+# CHECK-NEXT: 5.     1     0.0    0.0    0.0       vsetvli     zero, a0, e8, m2, tu, mu
+# CHECK-NEXT: 6.     1     0.0    0.0    0.0       vadd.vv     v12, v12, v12
+# CHECK-NEXT: 7.     1     0.0    0.0    0.0       vsub.vv     v12, v12, v12
+# CHECK-NEXT:        1     0.0    0.0    0.0       <total>

diff --git a/llvm/test/tools/llvm-mca/RISCV/riscv-instrument-no-data-is-err.s b/llvm/test/tools/llvm-mca/RISCV/riscv-instrument-no-data-is-err.s
new file mode 100644 (file)
index 0000000..ac5b0f8
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/riscv-instrument-no-data-is-err.s
@@ -0,0 +1,10 @@
+# RUN: not llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s 2>&1 | FileCheck %s
+
+vsetvli zero, a0, e8, m1, tu, mu
+# LLVM-MCA-RISCV-LMUL
+vadd.vv v12, v12, v12
+
+# CHECK: error: Failed to create RISCV-LMUL instrument with no data
+# CHECK: # LLVM-MCA-RISCV-LMUL
+# CHECK:  ^
+# CHECK: error: There was an error parsing comments.

diff --git a/llvm/test/tools/llvm-mca/RISCV/unknown-instrument-is-err.s b/llvm/test/tools/llvm-mca/RISCV/unknown-instrument-is-err.s
new file mode 100644 (file)
index 0000000..9067546
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/unknown-instrument-is-err.s
@@ -0,0 +1,10 @@
+# RUN: not llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s 2>&1 | FileCheck %s
+
+# LLVM-MCA-UNKNOWN M1
+vsetvli zero, a0, e8, m1, tu, mu
+vadd.vv v12, v12, v12
+
+# CHECK: error: Unknown instrumentation type in LLVM-MCA comment: UNKNOWN
+# CHECK: # LLVM-MCA-UNKNOWN M1
+# CHECK:  ^
+# CHECK:  error: There was an error parsing comments.

diff --git a/llvm/test/tools/llvm-mca/RISCV/unknown-lmul-is-err.s b/llvm/test/tools/llvm-mca/RISCV/unknown-lmul-is-err.s
new file mode 100644 (file)
index 0000000..ef08018
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/unknown-lmul-is-err.s
@@ -0,0 +1,10 @@
+# RUN: not llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s 2>&1 | FileCheck %s
+
+vsetvli zero, a0, e8, m1, tu, mu
+# LLVM-MCA-RISCV-V MF9
+vadd.vv v12, v12, v12
+
+# CHECK: error: Unknown instrumentation type in LLVM-MCA comment: RISCV-V
+# CHECK: # LLVM-MCA-RISCV-V MF9
+# CHECK:  ^
+# CHECK:  error: There was an error parsing comments.