+Mon Jun 21 14:58:42 1999 Nick Clifton <nickc@cygnus.com>
+
+ * config/arm/arm.h: Add cpp support for ARM920 and ARM920T cpu
+ types.
+
Mon Jun 21 06:22:21 1999 Mark Elbrecht <snowball3@bigfoot.com>
* i386/djgpp.h (LIB_SPEC): New.
/* True if we are currently building a constant table. */
int making_const_table;
-/* Define the information needed to generate branch insns. This is
+/* Define the information needed to generate branch insns. This is
stored from the compare operation. */
rtx arm_compare_op0, arm_compare_op1;
%{march=arm8:-D__ARM_ARCH_4__} \
%{march=arm810:-D__ARM_ARCH_4__} \
%{march=arm9:-D__ARM_ARCH_4T__} \
+%{march=arm920:-D__ARM_ARCH_4__} \
+%{march=arm920t:-D__ARM_ARCH_4T__} \
%{march=arm9tdmi:-D__ARM_ARCH_4T__} \
%{march=strongarm:-D__ARM_ARCH_4__} \
%{march=strongarm110:-D__ARM_ARCH_4__} \
%{mcpu=arm8:-D__ARM_ARCH_4__} \
%{mcpu=arm810:-D__ARM_ARCH_4__} \
%{mcpu=arm9:-D__ARM_ARCH_4T__} \
+ %{mcpu=arm920:-D__ARM_ARCH_4__} \
+ %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
%{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
%{mcpu=strongarm:-D__ARM_ARCH_4__} \
%{mcpu=strongarm110:-D__ARM_ARCH_4__} \
#define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
#define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
/* Note: TARGET_SHORT_BY_BYTES is really a misnomer. What it means is
- that short values sould not be accessed using word load instructions
+ that short values should not be accessed using word load instructions
as there is a possibility that they may not be word aligned and this
would generate an MMU fault. On processors which do not have a 16 bit
load instruction therefore, short values must be loaded by individual
;; Often the return insn will be the same as loading from memory, so set attr
(define_insn "return"
[(return)]
- "USE_RETURN_INSN(FALSE)"
+ "USE_RETURN_INSN (FALSE)"
"*
{
extern int arm_ccfsm_state;
[(match_operand 1 "cc_register" "") (const_int 0)])
(return)
(pc)))]
- "USE_RETURN_INSN(TRUE)"
+ "USE_RETURN_INSN (TRUE)"
"*
{
extern int arm_ccfsm_state;
[(match_operand 1 "cc_register" "") (const_int 0)])
(pc)
(return)))]
- "USE_RETURN_INSN(TRUE)"
+ "USE_RETURN_INSN (TRUE)"
"*
{
extern int arm_ccfsm_state;
(match_operand:SI 1 "general_operand" "g"))
(clobber (reg:SI 14))])
(return)]
- "(GET_CODE (operands[0]) == SYMBOL_REF && USE_RETURN_INSN(FALSE)
+ "(GET_CODE (operands[0]) == SYMBOL_REF && USE_RETURN_INSN (FALSE)
&& !get_frame_size () && !current_function_calls_alloca
&& !frame_pointer_needed && !current_function_args_size)"
"*
(match_operand:SI 2 "general_operand" "g")))
(clobber (reg:SI 14))])
(return)]
- "(GET_CODE (operands[1]) == SYMBOL_REF && USE_RETURN_INSN(FALSE)
+ "(GET_CODE (operands[1]) == SYMBOL_REF && USE_RETURN_INSN (FALSE)
&& !get_frame_size () && !current_function_calls_alloca
&& !frame_pointer_needed && !current_function_args_size)"
"*
(clobber (reg:SI 14))])
(use (match_dup 0))
(return)]
- "(GET_CODE (operands[1]) == SYMBOL_REF && USE_RETURN_INSN(FALSE)
+ "(GET_CODE (operands[1]) == SYMBOL_REF && USE_RETURN_INSN (FALSE)
&& !get_frame_size () && !current_function_calls_alloca
&& !frame_pointer_needed && !current_function_args_size)"
"*