PowerPC: remove branch prediction from rint implementation
authorAdhemerval Zanella <azanella@linux.vnet.ibm.com>
Fri, 29 Mar 2013 23:15:28 +0000 (18:15 -0500)
committerAdhemerval Zanella <azanella@linux.vnet.ibm.com>
Mon, 1 Apr 2013 11:36:51 +0000 (06:36 -0500)
The branch prediction hints is actually hurts performance in this case.
The assembly implementation make two assumptions: 1. 'fabs (x) < 2^52'
is unlikely and 2. 'x > 0.0' is unlike (if 1. is true). Since it a
general floating point function, expected input is not bounded and then
it is better to let the hardware handle the branches.

benchtests/Makefile
benchtests/rint-inputs [new file with mode: 0644]
sysdeps/powerpc/powerpc32/fpu/s_rint.S
sysdeps/powerpc/powerpc32/fpu/s_rintf.S
sysdeps/powerpc/powerpc64/fpu/s_rint.S
sysdeps/powerpc/powerpc64/fpu/s_rintf.S

index 74938b9..cc54b81 100644 (file)
@@ -43,7 +43,7 @@
 #   See pow-inputs for an example.
 
 subdir := benchtests
-bench := exp pow
+bench := exp pow rint
 
 exp-ITER = 100000
 exp-ARGLIST = double
@@ -55,5 +55,10 @@ pow-ARGLIST = double:double
 pow-RET = double
 LDFLAGS-bench-pow = -lm
 
+rint-ITER = 250000000
+rint-ARGLIST = double
+rint-RET = double
+LDFLAGS-bench-rint = -lm
+
 include ../Makeconfig
 include ../Rules
diff --git a/benchtests/rint-inputs b/benchtests/rint-inputs
new file mode 100644 (file)
index 0000000..a5f83dc
--- /dev/null
@@ -0,0 +1,4 @@
+78.5
+-78.5
+4503599627370497.0
+-4503599627370497.0
index f3cd036..f04055f 100644 (file)
@@ -45,14 +45,14 @@ ENTRY (__rint)
        fsub    fp12,fp13,fp13  /* generate 0.0  */
        fcmpu   cr7,fp0,fp13    /* if (fabs(x) > TWO52)  */
        fcmpu   cr6,fp1,fp12    /* if (x > 0.0)  */
-       bnllr-  cr7
-       bng-    cr6,.L4
+       bnllr   cr7
+       bng     cr6,.L4
        fadd    fp1,fp1,fp13    /* x+= TWO52;  */
        fsub    fp1,fp1,fp13    /* x-= TWO52;  */
        fabs    fp1,fp1         /* if (x == 0.0)  */
        blr                     /* x = 0.0; */
 .L4:
-       bnllr-  cr6             /* if (x < 0.0)  */
+       bnllr   cr6             /* if (x < 0.0)  */
        fsub    fp1,fp1,fp13    /* x-= TWO52;  */
        fadd    fp1,fp1,fp13    /* x+= TWO52;  */
        fnabs   fp1,fp1         /* if (x == 0.0)  */
index 247dd4a..e0301af 100644 (file)
@@ -41,14 +41,14 @@ ENTRY (__rintf)
        fsubs   fp12,fp13,fp13  /* generate 0.0  */
        fcmpu   cr7,fp0,fp13    /* if (fabs(x) > TWO23)  */
        fcmpu   cr6,fp1,fp12    /* if (x > 0.0)  */
-       bnllr-  cr7
-       bng-    cr6,.L4
+       bnllr   cr7
+       bng     cr6,.L4
        fadds   fp1,fp1,fp13    /* x+= TWO23;  */
        fsubs   fp1,fp1,fp13    /* x-= TWO23;  */
        fabs    fp1,fp1         /* if (x == 0.0)  */
        blr                     /* x = 0.0; */
 .L4:
-       bnllr-  cr6             /* if (x < 0.0)  */
+       bnllr   cr6             /* if (x < 0.0)  */
        fsubs   fp1,fp1,fp13    /* x-= TWO23;  */
        fadds   fp1,fp1,fp13    /* x+= TWO23;  */
        fnabs   fp1,fp1         /* if (x == 0.0)  */
index f333972..57e3759 100644 (file)
@@ -34,14 +34,14 @@ EALIGN (__rint, 4, 0)
        fsub    fp12,fp13,fp13  /* generate 0.0  */
        fcmpu   cr7,fp0,fp13    /* if (fabs(x) > TWO52)  */
        fcmpu   cr6,fp1,fp12    /* if (x > 0.0)  */
-       bnllr-  cr7
-       bng-    cr6,.L4
+       bnllr   cr7
+       bng     cr6,.L4
        fadd    fp1,fp1,fp13    /* x+= TWO52;  */
        fsub    fp1,fp1,fp13    /* x-= TWO52;  */
        fabs    fp1,fp1         /* if (x == 0.0)  */
        blr                     /* x = 0.0; */
 .L4:
-       bnllr-  cr6             /* if (x < 0.0)  */
+       bnllr   cr6             /* if (x < 0.0)  */
        fsub    fp1,fp1,fp13    /* x-= TWO52;  */
        fadd    fp1,fp1,fp13    /* x+= TWO52;  */
        fnabs   fp1,fp1         /* if (x == 0.0)  */
index 26b0872..cb28ec7 100644 (file)
@@ -30,14 +30,14 @@ EALIGN (__rintf, 4, 0)
        fsubs   fp12,fp13,fp13  /* generate 0.0  */
        fcmpu   cr7,fp0,fp13    /* if (fabs(x) > TWO23)  */
        fcmpu   cr6,fp1,fp12    /* if (x > 0.0)  */
-       bnllr-  cr7
-       bng-    cr6,.L4
+       bnllr   cr7
+       bng     cr6,.L4
        fadds   fp1,fp1,fp13    /* x+= TWO23;  */
        fsubs   fp1,fp1,fp13    /* x-= TWO23;  */
        fabs    fp1,fp1         /* if (x == 0.0)  */
        blr                     /* x = 0.0; */
 .L4:
-       bnllr-  cr6             /* if (x < 0.0)  */
+       bnllr   cr6             /* if (x < 0.0)  */
        fsubs   fp1,fp1,fp13    /* x-= TWO23;  */
        fadds   fp1,fp1,fp13    /* x+= TWO23;  */
        fnabs   fp1,fp1         /* if (x == 0.0)  */