return TailMBB;
}
-static MachineBasicBlock *
-emitVFCVT_RM_MASK(MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode) {
+static MachineBasicBlock *emitVFCVT_RM(MachineInstr &MI, MachineBasicBlock *BB,
+ unsigned Opcode) {
DebugLoc DL = MI.getDebugLoc();
const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
Register SavedFRM = MRI.createVirtualRegister(&RISCV::GPRRegClass);
+ assert(MI.getNumOperands() == 8 || MI.getNumOperands() == 7);
+ unsigned FRMIdx = MI.getNumOperands() == 8 ? 4 : 3;
+
// Update FRM and save the old value.
BuildMI(*BB, MI, DL, TII.get(RISCV::SwapFRMImm), SavedFRM)
- .addImm(MI.getOperand(4).getImm());
+ .addImm(MI.getOperand(FRMIdx).getImm());
// Emit an VFCVT without the FRM operand.
- assert(MI.getNumOperands() == 8);
- auto MIB = BuildMI(*BB, MI, DL, TII.get(Opcode))
- .add(MI.getOperand(0))
- .add(MI.getOperand(1))
- .add(MI.getOperand(2))
- .add(MI.getOperand(3))
- .add(MI.getOperand(5))
- .add(MI.getOperand(6))
- .add(MI.getOperand(7));
+ auto MIB = BuildMI(*BB, MI, DL, TII.get(Opcode));
+
+ for (unsigned I = 0; I < MI.getNumOperands(); I++)
+ if (I != FRMIdx)
+ MIB = MIB.add(MI.getOperand(I));
+
if (MI.getFlag(MachineInstr::MIFlag::NoFPExcept))
MIB->setFlag(MachineInstr::MIFlag::NoFPExcept);
Subtarget);
#define PseudoVFCVT_RM_LMUL_CASE(RMOpc, Opc, LMUL) \
+ case RISCV::RMOpc##_##LMUL: \
+ return emitVFCVT_RM(MI, BB, RISCV::Opc##_##LMUL); \
case RISCV::RMOpc##_##LMUL##_MASK: \
- return emitVFCVT_RM_MASK(MI, BB, RISCV::Opc##_##LMUL##_MASK);
+ return emitVFCVT_RM(MI, BB, RISCV::Opc##_##LMUL##_MASK);
#define PseudoVFCVT_RM_CASE(RMOpc, Opc) \
PseudoVFCVT_RM_LMUL_CASE(RMOpc, Opc, M1) \
let usesCustomInserter = 1;
}
+class VPseudoUnaryNoMask_FRM<VReg RetClass, VReg OpClass, string Constraint = ""> :
+ Pseudo<(outs RetClass:$rd),
+ (ins RetClass:$merge, OpClass:$rs2, ixlenimm:$frm, AVL:$vl,
+ ixlenimm:$sew, ixlenimm:$policy), []> {
+ let mayLoad = 0;
+ let mayStore = 0;
+ let hasSideEffects = 0;
+ let Constraints = !interleave([Constraint, "$rd = $merge"], ",");
+ let HasVLOp = 1;
+ let HasSEWOp = 1;
+ let HasVecPolicyOp = 1;
+ let usesCustomInserter = 1;
+}
+
class VPseudoUnaryMask_FRM<VReg RetClass, VReg OpClass, string Constraint = ""> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2,
LMULInfo MInfo,
string Constraint = ""> {
let VLMul = MInfo.value in {
- def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMask_FRM<RetClass, Op1Class,
+ def "_" # MInfo.MX : VPseudoUnaryNoMask_FRM<RetClass, Op1Class,
Constraint>;
+ def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMask_FRM<RetClass, Op1Class,
+ Constraint>,
+ RISCVMaskedPseudo</*MaskOpIdx*/ 2,
+ /*HasTU*/ false,
+ /*IsCombined*/true>;
}
}
;
; CHECK-F-LABEL: ctlz_nxv1i32:
; CHECK-F: # %bb.0:
-; CHECK-F-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-F-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-F-NEXT: vsrl.vi v8, v8, 23
; CHECK-F-NEXT: li a1, 158
; CHECK-F-NEXT: vrsub.vx v8, v8, a1
;
; CHECK-F-LABEL: ctlz_nxv2i32:
; CHECK-F: # %bb.0:
-; CHECK-F-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-F-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-F-NEXT: vsrl.vi v8, v8, 23
; CHECK-F-NEXT: li a1, 158
; CHECK-F-NEXT: vrsub.vx v8, v8, a1
;
; CHECK-F-LABEL: ctlz_nxv4i32:
; CHECK-F: # %bb.0:
-; CHECK-F-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-F-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-F-NEXT: vsrl.vi v8, v8, 23
; CHECK-F-NEXT: li a1, 158
; CHECK-F-NEXT: vrsub.vx v8, v8, a1
;
; CHECK-F-LABEL: ctlz_nxv8i32:
; CHECK-F: # %bb.0:
-; CHECK-F-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-F-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-F-NEXT: vsrl.vi v8, v8, 23
; CHECK-F-NEXT: li a1, 158
; CHECK-F-NEXT: vrsub.vx v8, v8, a1
;
; CHECK-F-LABEL: ctlz_nxv16i32:
; CHECK-F: # %bb.0:
-; CHECK-F-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-F-NEXT: vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-F-NEXT: vsrl.vi v8, v8, 23
; CHECK-F-NEXT: li a1, 158
; CHECK-F-NEXT: vrsub.vx v8, v8, a1
;
; CHECK-D-LABEL: ctlz_nxv16i32:
; CHECK-D: # %bb.0:
-; CHECK-D-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-D-NEXT: vmset.m v0
; CHECK-D-NEXT: fsrmi a0, 1
-; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-D-NEXT: vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-D-NEXT: vsrl.vi v8, v8, 23
; CHECK-D-NEXT: li a1, 158
; CHECK-D-NEXT: vrsub.vx v8, v8, a1
;
; CHECK-F-LABEL: ctlz_nxv1i64:
; CHECK-F: # %bb.0:
-; CHECK-F-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfncvt.f.xu.w v9, v8, v0.t
+; CHECK-F-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-F-NEXT: vfncvt.f.xu.w v9, v8
; CHECK-F-NEXT: vsrl.vi v8, v9, 23
; CHECK-F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-F-NEXT: vzext.vf2 v9, v8
;
; CHECK-D-LABEL: ctlz_nxv1i64:
; CHECK-D: # %bb.0:
-; CHECK-D-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; CHECK-D-NEXT: vmset.m v0
; CHECK-D-NEXT: fsrmi a0, 1
-; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-D-NEXT: vsetvli a1, zero, e64, m1, ta, ma
+; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-D-NEXT: li a1, 52
; CHECK-D-NEXT: vsrl.vx v8, v8, a1
; CHECK-D-NEXT: li a1, 1086
;
; CHECK-F-LABEL: ctlz_nxv2i64:
; CHECK-F: # %bb.0:
-; CHECK-F-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfncvt.f.xu.w v10, v8, v0.t
+; CHECK-F-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-F-NEXT: vfncvt.f.xu.w v10, v8
; CHECK-F-NEXT: vsrl.vi v8, v10, 23
; CHECK-F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-F-NEXT: vzext.vf2 v10, v8
;
; CHECK-D-LABEL: ctlz_nxv2i64:
; CHECK-D: # %bb.0:
-; CHECK-D-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; CHECK-D-NEXT: vmset.m v0
; CHECK-D-NEXT: fsrmi a0, 1
-; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-D-NEXT: vsetvli a1, zero, e64, m2, ta, ma
+; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-D-NEXT: li a1, 52
; CHECK-D-NEXT: vsrl.vx v8, v8, a1
; CHECK-D-NEXT: li a1, 1086
;
; CHECK-F-LABEL: ctlz_nxv4i64:
; CHECK-F: # %bb.0:
-; CHECK-F-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfncvt.f.xu.w v12, v8, v0.t
+; CHECK-F-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-F-NEXT: vfncvt.f.xu.w v12, v8
; CHECK-F-NEXT: vsrl.vi v8, v12, 23
; CHECK-F-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-F-NEXT: vzext.vf2 v12, v8
;
; CHECK-D-LABEL: ctlz_nxv4i64:
; CHECK-D: # %bb.0:
-; CHECK-D-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; CHECK-D-NEXT: vmset.m v0
; CHECK-D-NEXT: fsrmi a0, 1
-; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-D-NEXT: vsetvli a1, zero, e64, m4, ta, ma
+; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-D-NEXT: li a1, 52
; CHECK-D-NEXT: vsrl.vx v8, v8, a1
; CHECK-D-NEXT: li a1, 1086
;
; CHECK-F-LABEL: ctlz_nxv8i64:
; CHECK-F: # %bb.0:
-; CHECK-F-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfncvt.f.xu.w v16, v8, v0.t
+; CHECK-F-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-F-NEXT: vfncvt.f.xu.w v16, v8
; CHECK-F-NEXT: vsrl.vi v8, v16, 23
; CHECK-F-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-F-NEXT: vzext.vf2 v16, v8
;
; CHECK-D-LABEL: ctlz_nxv8i64:
; CHECK-D: # %bb.0:
-; CHECK-D-NEXT: vsetvli a0, zero, e64, m8, ta, ma
-; CHECK-D-NEXT: vmset.m v0
; CHECK-D-NEXT: fsrmi a0, 1
-; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-D-NEXT: vsetvli a1, zero, e64, m8, ta, ma
+; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-D-NEXT: li a1, 52
; CHECK-D-NEXT: vsrl.vx v8, v8, a1
; CHECK-D-NEXT: li a1, 1086
;
; CHECK-F-LABEL: ctlz_zero_undef_nxv1i32:
; CHECK-F: # %bb.0:
-; CHECK-F-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-F-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-F-NEXT: vsrl.vi v8, v8, 23
; CHECK-F-NEXT: li a1, 158
; CHECK-F-NEXT: vrsub.vx v8, v8, a1
;
; CHECK-F-LABEL: ctlz_zero_undef_nxv2i32:
; CHECK-F: # %bb.0:
-; CHECK-F-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-F-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-F-NEXT: vsrl.vi v8, v8, 23
; CHECK-F-NEXT: li a1, 158
; CHECK-F-NEXT: vrsub.vx v8, v8, a1
;
; CHECK-F-LABEL: ctlz_zero_undef_nxv4i32:
; CHECK-F: # %bb.0:
-; CHECK-F-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-F-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-F-NEXT: vsrl.vi v8, v8, 23
; CHECK-F-NEXT: li a1, 158
; CHECK-F-NEXT: vrsub.vx v8, v8, a1
;
; CHECK-F-LABEL: ctlz_zero_undef_nxv8i32:
; CHECK-F: # %bb.0:
-; CHECK-F-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-F-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-F-NEXT: vsrl.vi v8, v8, 23
; CHECK-F-NEXT: li a1, 158
; CHECK-F-NEXT: vrsub.vx v8, v8, a1
;
; CHECK-F-LABEL: ctlz_zero_undef_nxv16i32:
; CHECK-F: # %bb.0:
-; CHECK-F-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-F-NEXT: vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-F-NEXT: vsrl.vi v8, v8, 23
; CHECK-F-NEXT: li a1, 158
; CHECK-F-NEXT: vrsub.vx v8, v8, a1
;
; CHECK-D-LABEL: ctlz_zero_undef_nxv16i32:
; CHECK-D: # %bb.0:
-; CHECK-D-NEXT: vsetvli a0, zero, e32, m8, ta, ma
-; CHECK-D-NEXT: vmset.m v0
; CHECK-D-NEXT: fsrmi a0, 1
-; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-D-NEXT: vsetvli a1, zero, e32, m8, ta, ma
+; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-D-NEXT: vsrl.vi v8, v8, 23
; CHECK-D-NEXT: li a1, 158
; CHECK-D-NEXT: vrsub.vx v8, v8, a1
;
; CHECK-F-LABEL: ctlz_zero_undef_nxv1i64:
; CHECK-F: # %bb.0:
-; CHECK-F-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfncvt.f.xu.w v9, v8, v0.t
+; CHECK-F-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-F-NEXT: vfncvt.f.xu.w v9, v8
; CHECK-F-NEXT: vsrl.vi v8, v9, 23
; CHECK-F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-F-NEXT: vzext.vf2 v9, v8
;
; CHECK-D-LABEL: ctlz_zero_undef_nxv1i64:
; CHECK-D: # %bb.0:
-; CHECK-D-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; CHECK-D-NEXT: vmset.m v0
; CHECK-D-NEXT: fsrmi a0, 1
-; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-D-NEXT: vsetvli a1, zero, e64, m1, ta, ma
+; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-D-NEXT: li a1, 52
; CHECK-D-NEXT: vsrl.vx v8, v8, a1
; CHECK-D-NEXT: li a1, 1086
;
; CHECK-F-LABEL: ctlz_zero_undef_nxv2i64:
; CHECK-F: # %bb.0:
-; CHECK-F-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfncvt.f.xu.w v10, v8, v0.t
+; CHECK-F-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-F-NEXT: vfncvt.f.xu.w v10, v8
; CHECK-F-NEXT: vsrl.vi v8, v10, 23
; CHECK-F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-F-NEXT: vzext.vf2 v10, v8
;
; CHECK-D-LABEL: ctlz_zero_undef_nxv2i64:
; CHECK-D: # %bb.0:
-; CHECK-D-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; CHECK-D-NEXT: vmset.m v0
; CHECK-D-NEXT: fsrmi a0, 1
-; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-D-NEXT: vsetvli a1, zero, e64, m2, ta, ma
+; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-D-NEXT: li a1, 52
; CHECK-D-NEXT: vsrl.vx v8, v8, a1
; CHECK-D-NEXT: li a1, 1086
;
; CHECK-F-LABEL: ctlz_zero_undef_nxv4i64:
; CHECK-F: # %bb.0:
-; CHECK-F-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfncvt.f.xu.w v12, v8, v0.t
+; CHECK-F-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-F-NEXT: vfncvt.f.xu.w v12, v8
; CHECK-F-NEXT: vsrl.vi v8, v12, 23
; CHECK-F-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-F-NEXT: vzext.vf2 v12, v8
;
; CHECK-D-LABEL: ctlz_zero_undef_nxv4i64:
; CHECK-D: # %bb.0:
-; CHECK-D-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; CHECK-D-NEXT: vmset.m v0
; CHECK-D-NEXT: fsrmi a0, 1
-; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-D-NEXT: vsetvli a1, zero, e64, m4, ta, ma
+; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-D-NEXT: li a1, 52
; CHECK-D-NEXT: vsrl.vx v8, v8, a1
; CHECK-D-NEXT: li a1, 1086
;
; CHECK-F-LABEL: ctlz_zero_undef_nxv8i64:
; CHECK-F: # %bb.0:
-; CHECK-F-NEXT: vsetvli a0, zero, e32, m4, ta, ma
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfncvt.f.xu.w v16, v8, v0.t
+; CHECK-F-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-F-NEXT: vfncvt.f.xu.w v16, v8
; CHECK-F-NEXT: vsrl.vi v8, v16, 23
; CHECK-F-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-F-NEXT: vzext.vf2 v16, v8
;
; CHECK-D-LABEL: ctlz_zero_undef_nxv8i64:
; CHECK-D: # %bb.0:
-; CHECK-D-NEXT: vsetvli a0, zero, e64, m8, ta, ma
-; CHECK-D-NEXT: vmset.m v0
; CHECK-D-NEXT: fsrmi a0, 1
-; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-D-NEXT: vsetvli a1, zero, e64, m8, ta, ma
+; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-D-NEXT: li a1, 52
; CHECK-D-NEXT: vsrl.vx v8, v8, a1
; CHECK-D-NEXT: li a1, 1086
; CHECK-F-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-F-NEXT: vrsub.vi v9, v8, 0
; CHECK-F-NEXT: vand.vv v9, v8, v9
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfcvt.f.xu.v v9, v9, v0.t
+; CHECK-F-NEXT: vfcvt.f.xu.v v9, v9
; CHECK-F-NEXT: vsrl.vi v9, v9, 23
; CHECK-F-NEXT: li a1, 127
; CHECK-F-NEXT: vsub.vx v9, v9, a1
; CHECK-F-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-F-NEXT: vrsub.vi v9, v8, 0
; CHECK-F-NEXT: vand.vv v9, v8, v9
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfcvt.f.xu.v v9, v9, v0.t
+; CHECK-F-NEXT: vfcvt.f.xu.v v9, v9
; CHECK-F-NEXT: vsrl.vi v9, v9, 23
; CHECK-F-NEXT: li a1, 127
; CHECK-F-NEXT: vsub.vx v9, v9, a1
; CHECK-F-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-F-NEXT: vrsub.vi v10, v8, 0
; CHECK-F-NEXT: vand.vv v10, v8, v10
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfcvt.f.xu.v v10, v10, v0.t
+; CHECK-F-NEXT: vfcvt.f.xu.v v10, v10
; CHECK-F-NEXT: vsrl.vi v10, v10, 23
; CHECK-F-NEXT: li a1, 127
; CHECK-F-NEXT: vsub.vx v10, v10, a1
; CHECK-F-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-F-NEXT: vrsub.vi v12, v8, 0
; CHECK-F-NEXT: vand.vv v12, v8, v12
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfcvt.f.xu.v v12, v12, v0.t
+; CHECK-F-NEXT: vfcvt.f.xu.v v12, v12
; CHECK-F-NEXT: vsrl.vi v12, v12, 23
; CHECK-F-NEXT: li a1, 127
; CHECK-F-NEXT: vsub.vx v12, v12, a1
; CHECK-F-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-F-NEXT: vrsub.vi v16, v8, 0
; CHECK-F-NEXT: vand.vv v16, v8, v16
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfcvt.f.xu.v v16, v16, v0.t
+; CHECK-F-NEXT: vfcvt.f.xu.v v16, v16
; CHECK-F-NEXT: vsrl.vi v16, v16, 23
; CHECK-F-NEXT: li a1, 127
; CHECK-F-NEXT: vsub.vx v16, v16, a1
; CHECK-D-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-D-NEXT: vrsub.vi v16, v8, 0
; CHECK-D-NEXT: vand.vv v16, v8, v16
-; CHECK-D-NEXT: vmset.m v0
; CHECK-D-NEXT: fsrmi a0, 1
-; CHECK-D-NEXT: vfcvt.f.xu.v v16, v16, v0.t
+; CHECK-D-NEXT: vfcvt.f.xu.v v16, v16
; CHECK-D-NEXT: vsrl.vi v16, v16, 23
; CHECK-D-NEXT: li a1, 127
; CHECK-D-NEXT: vsub.vx v16, v16, a1
; RV32F-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32F-NEXT: vrsub.vi v9, v8, 0
; RV32F-NEXT: vand.vv v9, v8, v9
-; RV32F-NEXT: vmset.m v0
; RV32F-NEXT: fsrmi a0, 1
; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v10, v9, v0.t
+; RV32F-NEXT: vfncvt.f.xu.w v10, v9
; RV32F-NEXT: vsrl.vi v9, v10, 23
; RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV32F-NEXT: vzext.vf2 v10, v9
; RV64F-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV64F-NEXT: vrsub.vi v9, v8, 0
; RV64F-NEXT: vand.vv v9, v8, v9
-; RV64F-NEXT: vmset.m v0
; RV64F-NEXT: fsrmi a0, 1
; RV64F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV64F-NEXT: vfncvt.f.xu.w v10, v9, v0.t
+; RV64F-NEXT: vfncvt.f.xu.w v10, v9
; RV64F-NEXT: vsrl.vi v9, v10, 23
; RV64F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; RV64F-NEXT: vzext.vf2 v10, v9
; RV32D-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV32D-NEXT: vrsub.vi v9, v8, 0
; RV32D-NEXT: vand.vv v9, v8, v9
-; RV32D-NEXT: vmset.m v0
; RV32D-NEXT: fsrmi a0, 1
-; RV32D-NEXT: vfcvt.f.xu.v v9, v9, v0.t
+; RV32D-NEXT: vfcvt.f.xu.v v9, v9
; RV32D-NEXT: li a1, 52
; RV32D-NEXT: vsrl.vx v9, v9, a1
; RV32D-NEXT: li a1, 1023
; RV64D-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; RV64D-NEXT: vrsub.vi v9, v8, 0
; RV64D-NEXT: vand.vv v9, v8, v9
-; RV64D-NEXT: vmset.m v0
; RV64D-NEXT: fsrmi a0, 1
-; RV64D-NEXT: vfcvt.f.xu.v v9, v9, v0.t
+; RV64D-NEXT: vfcvt.f.xu.v v9, v9
; RV64D-NEXT: li a1, 52
; RV64D-NEXT: vsrl.vx v9, v9, a1
; RV64D-NEXT: li a1, 1023
; RV32F-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; RV32F-NEXT: vrsub.vi v10, v8, 0
; RV32F-NEXT: vand.vv v10, v8, v10
-; RV32F-NEXT: vmset.m v0
; RV32F-NEXT: fsrmi a0, 1
; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v12, v10, v0.t
+; RV32F-NEXT: vfncvt.f.xu.w v12, v10
; RV32F-NEXT: vsrl.vi v10, v12, 23
; RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV32F-NEXT: vzext.vf2 v12, v10
; RV64F-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; RV64F-NEXT: vrsub.vi v10, v8, 0
; RV64F-NEXT: vand.vv v10, v8, v10
-; RV64F-NEXT: vmset.m v0
; RV64F-NEXT: fsrmi a0, 1
; RV64F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64F-NEXT: vfncvt.f.xu.w v12, v10, v0.t
+; RV64F-NEXT: vfncvt.f.xu.w v12, v10
; RV64F-NEXT: vsrl.vi v10, v12, 23
; RV64F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; RV64F-NEXT: vzext.vf2 v12, v10
; RV32D-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; RV32D-NEXT: vrsub.vi v10, v8, 0
; RV32D-NEXT: vand.vv v10, v8, v10
-; RV32D-NEXT: vmset.m v0
; RV32D-NEXT: fsrmi a0, 1
-; RV32D-NEXT: vfcvt.f.xu.v v10, v10, v0.t
+; RV32D-NEXT: vfcvt.f.xu.v v10, v10
; RV32D-NEXT: li a1, 52
; RV32D-NEXT: vsrl.vx v10, v10, a1
; RV32D-NEXT: li a1, 1023
; RV64D-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; RV64D-NEXT: vrsub.vi v10, v8, 0
; RV64D-NEXT: vand.vv v10, v8, v10
-; RV64D-NEXT: vmset.m v0
; RV64D-NEXT: fsrmi a0, 1
-; RV64D-NEXT: vfcvt.f.xu.v v10, v10, v0.t
+; RV64D-NEXT: vfcvt.f.xu.v v10, v10
; RV64D-NEXT: li a1, 52
; RV64D-NEXT: vsrl.vx v10, v10, a1
; RV64D-NEXT: li a1, 1023
; RV32F-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV32F-NEXT: vrsub.vi v12, v8, 0
; RV32F-NEXT: vand.vv v12, v8, v12
-; RV32F-NEXT: vmset.m v0
; RV32F-NEXT: fsrmi a0, 1
; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v16, v12, v0.t
+; RV32F-NEXT: vfncvt.f.xu.w v16, v12
; RV32F-NEXT: vsrl.vi v12, v16, 23
; RV32F-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV32F-NEXT: vzext.vf2 v16, v12
; RV64F-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV64F-NEXT: vrsub.vi v12, v8, 0
; RV64F-NEXT: vand.vv v12, v8, v12
-; RV64F-NEXT: vmset.m v0
; RV64F-NEXT: fsrmi a0, 1
; RV64F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV64F-NEXT: vfncvt.f.xu.w v16, v12, v0.t
+; RV64F-NEXT: vfncvt.f.xu.w v16, v12
; RV64F-NEXT: vsrl.vi v12, v16, 23
; RV64F-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV64F-NEXT: vzext.vf2 v16, v12
; RV32D-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV32D-NEXT: vrsub.vi v12, v8, 0
; RV32D-NEXT: vand.vv v12, v8, v12
-; RV32D-NEXT: vmset.m v0
; RV32D-NEXT: fsrmi a0, 1
-; RV32D-NEXT: vfcvt.f.xu.v v12, v12, v0.t
+; RV32D-NEXT: vfcvt.f.xu.v v12, v12
; RV32D-NEXT: li a1, 52
; RV32D-NEXT: vsrl.vx v12, v12, a1
; RV32D-NEXT: li a1, 1023
; RV64D-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; RV64D-NEXT: vrsub.vi v12, v8, 0
; RV64D-NEXT: vand.vv v12, v8, v12
-; RV64D-NEXT: vmset.m v0
; RV64D-NEXT: fsrmi a0, 1
-; RV64D-NEXT: vfcvt.f.xu.v v12, v12, v0.t
+; RV64D-NEXT: vfcvt.f.xu.v v12, v12
; RV64D-NEXT: li a1, 52
; RV64D-NEXT: vsrl.vx v12, v12, a1
; RV64D-NEXT: li a1, 1023
; RV32F-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV32F-NEXT: vrsub.vi v16, v8, 0
; RV32F-NEXT: vand.vv v16, v8, v16
-; RV32F-NEXT: vmset.m v0
; RV32F-NEXT: fsrmi a0, 1
; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v24, v16, v0.t
+; RV32F-NEXT: vfncvt.f.xu.w v24, v16
; RV32F-NEXT: vsrl.vi v16, v24, 23
; RV32F-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV32F-NEXT: vzext.vf2 v24, v16
; RV64F-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV64F-NEXT: vrsub.vi v16, v8, 0
; RV64F-NEXT: vand.vv v16, v8, v16
-; RV64F-NEXT: vmset.m v0
; RV64F-NEXT: fsrmi a0, 1
; RV64F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64F-NEXT: vfncvt.f.xu.w v24, v16, v0.t
+; RV64F-NEXT: vfncvt.f.xu.w v24, v16
; RV64F-NEXT: vsrl.vi v16, v24, 23
; RV64F-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; RV64F-NEXT: vzext.vf2 v24, v16
; RV32D-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV32D-NEXT: vrsub.vi v16, v8, 0
; RV32D-NEXT: vand.vv v16, v8, v16
-; RV32D-NEXT: vmset.m v0
; RV32D-NEXT: fsrmi a0, 1
-; RV32D-NEXT: vfcvt.f.xu.v v16, v16, v0.t
+; RV32D-NEXT: vfcvt.f.xu.v v16, v16
; RV32D-NEXT: li a1, 52
; RV32D-NEXT: vsrl.vx v16, v16, a1
; RV32D-NEXT: li a1, 1023
; RV64D-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV64D-NEXT: vrsub.vi v16, v8, 0
; RV64D-NEXT: vand.vv v16, v8, v16
-; RV64D-NEXT: vmset.m v0
; RV64D-NEXT: fsrmi a0, 1
-; RV64D-NEXT: vfcvt.f.xu.v v16, v16, v0.t
+; RV64D-NEXT: vfcvt.f.xu.v v16, v16
; RV64D-NEXT: li a1, 52
; RV64D-NEXT: vsrl.vx v16, v16, a1
; RV64D-NEXT: li a1, 1023
; CHECK-F-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-F-NEXT: vrsub.vi v9, v8, 0
; CHECK-F-NEXT: vand.vv v8, v8, v9
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-F-NEXT: vsrl.vi v8, v8, 23
; CHECK-F-NEXT: li a1, 127
; CHECK-F-NEXT: vsub.vx v8, v8, a1
; CHECK-F-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-F-NEXT: vrsub.vi v9, v8, 0
; CHECK-F-NEXT: vand.vv v8, v8, v9
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-F-NEXT: vsrl.vi v8, v8, 23
; CHECK-F-NEXT: li a1, 127
; CHECK-F-NEXT: vsub.vx v8, v8, a1
; CHECK-F-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-F-NEXT: vrsub.vi v10, v8, 0
; CHECK-F-NEXT: vand.vv v8, v8, v10
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-F-NEXT: vsrl.vi v8, v8, 23
; CHECK-F-NEXT: li a1, 127
; CHECK-F-NEXT: vsub.vx v8, v8, a1
; CHECK-F-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-F-NEXT: vrsub.vi v12, v8, 0
; CHECK-F-NEXT: vand.vv v8, v8, v12
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-F-NEXT: vsrl.vi v8, v8, 23
; CHECK-F-NEXT: li a1, 127
; CHECK-F-NEXT: vsub.vx v8, v8, a1
; CHECK-F-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-F-NEXT: vrsub.vi v16, v8, 0
; CHECK-F-NEXT: vand.vv v8, v8, v16
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
-; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-F-NEXT: vsrl.vi v8, v8, 23
; CHECK-F-NEXT: li a1, 127
; CHECK-F-NEXT: vsub.vx v8, v8, a1
; CHECK-D-NEXT: vsetvli a0, zero, e32, m8, ta, ma
; CHECK-D-NEXT: vrsub.vi v16, v8, 0
; CHECK-D-NEXT: vand.vv v8, v8, v16
-; CHECK-D-NEXT: vmset.m v0
; CHECK-D-NEXT: fsrmi a0, 1
-; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-D-NEXT: vsrl.vi v8, v8, 23
; CHECK-D-NEXT: li a1, 127
; CHECK-D-NEXT: vsub.vx v8, v8, a1
; CHECK-F-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-F-NEXT: vrsub.vi v9, v8, 0
; CHECK-F-NEXT: vand.vv v8, v8, v9
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
; CHECK-F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; CHECK-F-NEXT: vfncvt.f.xu.w v9, v8, v0.t
+; CHECK-F-NEXT: vfncvt.f.xu.w v9, v8
; CHECK-F-NEXT: vsrl.vi v8, v9, 23
; CHECK-F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-F-NEXT: vzext.vf2 v9, v8
; CHECK-D-NEXT: vsetvli a0, zero, e64, m1, ta, ma
; CHECK-D-NEXT: vrsub.vi v9, v8, 0
; CHECK-D-NEXT: vand.vv v8, v8, v9
-; CHECK-D-NEXT: vmset.m v0
; CHECK-D-NEXT: fsrmi a0, 1
-; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-D-NEXT: li a1, 52
; CHECK-D-NEXT: vsrl.vx v8, v8, a1
; CHECK-D-NEXT: li a1, 1023
; CHECK-F-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-F-NEXT: vrsub.vi v10, v8, 0
; CHECK-F-NEXT: vand.vv v8, v8, v10
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
; CHECK-F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; CHECK-F-NEXT: vfncvt.f.xu.w v10, v8, v0.t
+; CHECK-F-NEXT: vfncvt.f.xu.w v10, v8
; CHECK-F-NEXT: vsrl.vi v8, v10, 23
; CHECK-F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-F-NEXT: vzext.vf2 v10, v8
; CHECK-D-NEXT: vsetvli a0, zero, e64, m2, ta, ma
; CHECK-D-NEXT: vrsub.vi v10, v8, 0
; CHECK-D-NEXT: vand.vv v8, v8, v10
-; CHECK-D-NEXT: vmset.m v0
; CHECK-D-NEXT: fsrmi a0, 1
-; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-D-NEXT: li a1, 52
; CHECK-D-NEXT: vsrl.vx v8, v8, a1
; CHECK-D-NEXT: li a1, 1023
; CHECK-F-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-F-NEXT: vrsub.vi v12, v8, 0
; CHECK-F-NEXT: vand.vv v8, v8, v12
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
; CHECK-F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; CHECK-F-NEXT: vfncvt.f.xu.w v12, v8, v0.t
+; CHECK-F-NEXT: vfncvt.f.xu.w v12, v8
; CHECK-F-NEXT: vsrl.vi v8, v12, 23
; CHECK-F-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-F-NEXT: vzext.vf2 v12, v8
; CHECK-D-NEXT: vsetvli a0, zero, e64, m4, ta, ma
; CHECK-D-NEXT: vrsub.vi v12, v8, 0
; CHECK-D-NEXT: vand.vv v8, v8, v12
-; CHECK-D-NEXT: vmset.m v0
; CHECK-D-NEXT: fsrmi a0, 1
-; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-D-NEXT: li a1, 52
; CHECK-D-NEXT: vsrl.vx v8, v8, a1
; CHECK-D-NEXT: li a1, 1023
; CHECK-F-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-F-NEXT: vrsub.vi v16, v8, 0
; CHECK-F-NEXT: vand.vv v8, v8, v16
-; CHECK-F-NEXT: vmset.m v0
; CHECK-F-NEXT: fsrmi a0, 1
; CHECK-F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; CHECK-F-NEXT: vfncvt.f.xu.w v16, v8, v0.t
+; CHECK-F-NEXT: vfncvt.f.xu.w v16, v8
; CHECK-F-NEXT: vsrl.vi v8, v16, 23
; CHECK-F-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-F-NEXT: vzext.vf2 v16, v8
; CHECK-D-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-D-NEXT: vrsub.vi v16, v8, 0
; CHECK-D-NEXT: vand.vv v8, v8, v16
-; CHECK-D-NEXT: vmset.m v0
; CHECK-D-NEXT: fsrmi a0, 1
-; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8
; CHECK-D-NEXT: li a1, 52
; CHECK-D-NEXT: vsrl.vx v8, v8, a1
; CHECK-D-NEXT: li a1, 1023
define <vscale x 1 x i32> @ceil_nxv1f64_to_si32(<vscale x 1 x double> %x) {
; RV32-LABEL: ceil_nxv1f64_to_si32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfncvt.x.f.w v9, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; RV32-NEXT: vfncvt.x.f.w v9, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv1f64_to_si32:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfncvt.x.f.w v9, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; RV64-NEXT: vfncvt.x.f.w v9, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
define <vscale x 1 x i32> @ceil_nxv1f64_to_ui32(<vscale x 1 x double> %x) {
; RV32-LABEL: ceil_nxv1f64_to_ui32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfncvt.xu.f.w v9, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; RV32-NEXT: vfncvt.xu.f.w v9, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv1f64_to_ui32:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfncvt.xu.f.w v9, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; RV64-NEXT: vfncvt.xu.f.w v9, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
define <vscale x 1 x i64> @ceil_nxv1f64_to_si64(<vscale x 1 x double> %x) {
; RV32-LABEL: ceil_nxv1f64_to_si64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv1f64_to_si64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
+; RV64-NEXT: vfcvt.x.f.v v8, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: ret
%a = call <vscale x 1 x double> @llvm.ceil.nxv1f64(<vscale x 1 x double> %x)
define <vscale x 1 x i64> @ceil_nxv1f64_to_ui64(<vscale x 1 x double> %x) {
; RV32-LABEL: ceil_nxv1f64_to_ui64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfcvt.xu.f.v v8, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma
+; RV32-NEXT: vfcvt.xu.f.v v8, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv1f64_to_ui64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfcvt.xu.f.v v8, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma
+; RV64-NEXT: vfcvt.xu.f.v v8, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: ret
%a = call <vscale x 1 x double> @llvm.ceil.nxv1f64(<vscale x 1 x double> %x)
define <vscale x 4 x i32> @ceil_nxv4f64_to_si32(<vscale x 4 x double> %x) {
; RV32-LABEL: ceil_nxv4f64_to_si32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfncvt.x.f.w v12, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; RV32-NEXT: vfncvt.x.f.w v12, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv4f64_to_si32:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfncvt.x.f.w v12, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; RV64-NEXT: vfncvt.x.f.w v12, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: vmv.v.v v8, v12
; RV64-NEXT: ret
define <vscale x 4 x i32> @ceil_nxv4f64_to_ui32(<vscale x 4 x double> %x) {
; RV32-LABEL: ceil_nxv4f64_to_ui32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfncvt.xu.f.w v12, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; RV32-NEXT: vfncvt.xu.f.w v12, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv4f64_to_ui32:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfncvt.xu.f.w v12, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; RV64-NEXT: vfncvt.xu.f.w v12, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: vmv.v.v v8, v12
; RV64-NEXT: ret
define <vscale x 4 x i64> @ceil_nxv4f64_to_si64(<vscale x 4 x double> %x) {
; RV32-LABEL: ceil_nxv4f64_to_si64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv4f64_to_si64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma
+; RV64-NEXT: vfcvt.x.f.v v8, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: ret
%a = call <vscale x 4 x double> @llvm.ceil.nxv4f64(<vscale x 4 x double> %x)
define <vscale x 4 x i64> @ceil_nxv4f64_to_ui64(<vscale x 4 x double> %x) {
; RV32-LABEL: ceil_nxv4f64_to_ui64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfcvt.xu.f.v v8, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma
+; RV32-NEXT: vfcvt.xu.f.v v8, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv4f64_to_ui64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfcvt.xu.f.v v8, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma
+; RV64-NEXT: vfcvt.xu.f.v v8, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: ret
%a = call <vscale x 4 x double> @llvm.ceil.nxv4f64(<vscale x 4 x double> %x)
; LMULMAX2-RV32F: # %bb.0:
; LMULMAX2-RV32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX2-RV32F-NEXT: vle32.v v8, (a0)
-; LMULMAX2-RV32F-NEXT: vmset.m v0
; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
-; LMULMAX2-RV32F-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; LMULMAX2-RV32F-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX2-RV32F-NEXT: fsrm a1
; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v8, 23
; LMULMAX2-RV32F-NEXT: li a1, 158
; LMULMAX2-RV64F: # %bb.0:
; LMULMAX2-RV64F-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX2-RV64F-NEXT: vle32.v v8, (a0)
-; LMULMAX2-RV64F-NEXT: vmset.m v0
; LMULMAX2-RV64F-NEXT: fsrmi a1, 1
-; LMULMAX2-RV64F-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; LMULMAX2-RV64F-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX2-RV64F-NEXT: fsrm a1
; LMULMAX2-RV64F-NEXT: vsrl.vi v8, v8, 23
; LMULMAX2-RV64F-NEXT: li a1, 158
;
; LMULMAX2-RV32F-LABEL: ctlz_v2i64:
; LMULMAX2-RV32F: # %bb.0:
-; LMULMAX2-RV32F-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; LMULMAX2-RV32F-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX2-RV32F-NEXT: vle64.v v8, (a0)
-; LMULMAX2-RV32F-NEXT: vmset.m v0
-; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
-; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v9, v8, v0.t
-; LMULMAX2-RV32F-NEXT: fsrm a1
-; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v9, 23
; LMULMAX2-RV32F-NEXT: li a1, 190
-; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; LMULMAX2-RV32F-NEXT: vmv.v.x v9, a1
+; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v10, v8
+; LMULMAX2-RV32F-NEXT: fsrm a1
+; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v10, 23
; LMULMAX2-RV32F-NEXT: vwsubu.wv v9, v9, v8
; LMULMAX2-RV32F-NEXT: li a1, 64
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; LMULMAX2-RV64F: # %bb.0:
; LMULMAX2-RV64F-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; LMULMAX2-RV64F-NEXT: vle64.v v8, (a0)
-; LMULMAX2-RV64F-NEXT: vmset.m v0
-; LMULMAX2-RV64F-NEXT: fsrmi a1, 1
-; LMULMAX2-RV64F-NEXT: vfncvt.f.xu.w v9, v8, v0.t
-; LMULMAX2-RV64F-NEXT: fsrm a1
-; LMULMAX2-RV64F-NEXT: vsrl.vi v8, v9, 23
; LMULMAX2-RV64F-NEXT: li a1, 190
; LMULMAX2-RV64F-NEXT: vmv.v.x v9, a1
+; LMULMAX2-RV64F-NEXT: fsrmi a1, 1
+; LMULMAX2-RV64F-NEXT: vfncvt.f.xu.w v10, v8
+; LMULMAX2-RV64F-NEXT: fsrm a1
+; LMULMAX2-RV64F-NEXT: vsrl.vi v8, v10, 23
; LMULMAX2-RV64F-NEXT: vwsubu.vv v10, v9, v8
; LMULMAX2-RV64F-NEXT: li a1, 64
; LMULMAX2-RV64F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; LMULMAX2-RV32D: # %bb.0:
; LMULMAX2-RV32D-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX2-RV32D-NEXT: vle64.v v8, (a0)
-; LMULMAX2-RV32D-NEXT: vmset.m v0
; LMULMAX2-RV32D-NEXT: fsrmi a1, 1
-; LMULMAX2-RV32D-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; LMULMAX2-RV32D-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX2-RV32D-NEXT: fsrm a1
; LMULMAX2-RV32D-NEXT: li a1, 52
; LMULMAX2-RV32D-NEXT: vsrl.vx v8, v8, a1
; LMULMAX2-RV64D: # %bb.0:
; LMULMAX2-RV64D-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX2-RV64D-NEXT: vle64.v v8, (a0)
-; LMULMAX2-RV64D-NEXT: vmset.m v0
; LMULMAX2-RV64D-NEXT: fsrmi a1, 1
-; LMULMAX2-RV64D-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; LMULMAX2-RV64D-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX2-RV64D-NEXT: fsrm a1
; LMULMAX2-RV64D-NEXT: li a1, 52
; LMULMAX2-RV64D-NEXT: vsrl.vx v8, v8, a1
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; LMULMAX8-NEXT: vle64.v v8, (a0)
-; LMULMAX8-NEXT: vmset.m v0
; LMULMAX8-NEXT: fsrmi a1, 1
-; LMULMAX8-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; LMULMAX8-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX8-NEXT: fsrm a1
; LMULMAX8-NEXT: li a1, 52
; LMULMAX8-NEXT: vsrl.vx v8, v8, a1
; LMULMAX2-RV32F: # %bb.0:
; LMULMAX2-RV32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32F-NEXT: vle32.v v8, (a0)
-; LMULMAX2-RV32F-NEXT: vmset.m v0
; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
-; LMULMAX2-RV32F-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; LMULMAX2-RV32F-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX2-RV32F-NEXT: fsrm a1
; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v8, 23
; LMULMAX2-RV32F-NEXT: li a1, 158
; LMULMAX2-RV64F: # %bb.0:
; LMULMAX2-RV64F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV64F-NEXT: vle32.v v8, (a0)
-; LMULMAX2-RV64F-NEXT: vmset.m v0
; LMULMAX2-RV64F-NEXT: fsrmi a1, 1
-; LMULMAX2-RV64F-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; LMULMAX2-RV64F-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX2-RV64F-NEXT: fsrm a1
; LMULMAX2-RV64F-NEXT: vsrl.vi v8, v8, 23
; LMULMAX2-RV64F-NEXT: li a1, 158
; LMULMAX2-RV32D: # %bb.0:
; LMULMAX2-RV32D-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV32D-NEXT: vle32.v v8, (a0)
-; LMULMAX2-RV32D-NEXT: vmset.m v0
; LMULMAX2-RV32D-NEXT: fsrmi a1, 1
-; LMULMAX2-RV32D-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; LMULMAX2-RV32D-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX2-RV32D-NEXT: fsrm a1
; LMULMAX2-RV32D-NEXT: vsrl.vi v8, v8, 23
; LMULMAX2-RV32D-NEXT: li a1, 158
; LMULMAX2-RV64D: # %bb.0:
; LMULMAX2-RV64D-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; LMULMAX2-RV64D-NEXT: vle32.v v8, (a0)
-; LMULMAX2-RV64D-NEXT: vmset.m v0
; LMULMAX2-RV64D-NEXT: fsrmi a1, 1
-; LMULMAX2-RV64D-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; LMULMAX2-RV64D-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX2-RV64D-NEXT: fsrm a1
; LMULMAX2-RV64D-NEXT: vsrl.vi v8, v8, 23
; LMULMAX2-RV64D-NEXT: li a1, 158
;
; LMULMAX2-RV32F-LABEL: ctlz_v4i64:
; LMULMAX2-RV32F: # %bb.0:
-; LMULMAX2-RV32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; LMULMAX2-RV32F-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32F-NEXT: vle64.v v8, (a0)
-; LMULMAX2-RV32F-NEXT: vmset.m v0
-; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
-; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v10, v8, v0.t
-; LMULMAX2-RV32F-NEXT: fsrm a1
-; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v10, 23
; LMULMAX2-RV32F-NEXT: li a1, 190
-; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; LMULMAX2-RV32F-NEXT: vmv.v.x v10, a1
+; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v12, v8
+; LMULMAX2-RV32F-NEXT: fsrm a1
+; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v12, 23
; LMULMAX2-RV32F-NEXT: vwsubu.wv v10, v10, v8
; LMULMAX2-RV32F-NEXT: li a1, 64
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; LMULMAX2-RV64F: # %bb.0:
; LMULMAX2-RV64F-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; LMULMAX2-RV64F-NEXT: vle64.v v8, (a0)
-; LMULMAX2-RV64F-NEXT: vmset.m v0
+; LMULMAX2-RV64F-NEXT: li a1, 190
+; LMULMAX2-RV64F-NEXT: vmv.v.x v10, a1
; LMULMAX2-RV64F-NEXT: fsrmi a1, 1
-; LMULMAX2-RV64F-NEXT: vfncvt.f.xu.w v10, v8, v0.t
+; LMULMAX2-RV64F-NEXT: vfncvt.f.xu.w v11, v8
; LMULMAX2-RV64F-NEXT: fsrm a1
-; LMULMAX2-RV64F-NEXT: vsrl.vi v8, v10, 23
-; LMULMAX2-RV64F-NEXT: li a1, 190
-; LMULMAX2-RV64F-NEXT: vmv.v.x v9, a1
-; LMULMAX2-RV64F-NEXT: vwsubu.vv v10, v9, v8
+; LMULMAX2-RV64F-NEXT: vsrl.vi v8, v11, 23
+; LMULMAX2-RV64F-NEXT: vwsubu.vv v12, v10, v8
; LMULMAX2-RV64F-NEXT: li a1, 64
; LMULMAX2-RV64F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; LMULMAX2-RV64F-NEXT: vminu.vx v8, v10, a1
+; LMULMAX2-RV64F-NEXT: vminu.vx v8, v12, a1
; LMULMAX2-RV64F-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV64F-NEXT: ret
;
; LMULMAX2-RV32D: # %bb.0:
; LMULMAX2-RV32D-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV32D-NEXT: vle64.v v8, (a0)
-; LMULMAX2-RV32D-NEXT: vmset.m v0
; LMULMAX2-RV32D-NEXT: fsrmi a1, 1
-; LMULMAX2-RV32D-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; LMULMAX2-RV32D-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX2-RV32D-NEXT: fsrm a1
; LMULMAX2-RV32D-NEXT: li a1, 52
; LMULMAX2-RV32D-NEXT: vsrl.vx v8, v8, a1
; LMULMAX2-RV64D: # %bb.0:
; LMULMAX2-RV64D-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX2-RV64D-NEXT: vle64.v v8, (a0)
-; LMULMAX2-RV64D-NEXT: vmset.m v0
; LMULMAX2-RV64D-NEXT: fsrmi a1, 1
-; LMULMAX2-RV64D-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; LMULMAX2-RV64D-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX2-RV64D-NEXT: fsrm a1
; LMULMAX2-RV64D-NEXT: li a1, 52
; LMULMAX2-RV64D-NEXT: vsrl.vx v8, v8, a1
; LMULMAX8: # %bb.0:
; LMULMAX8-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; LMULMAX8-NEXT: vle64.v v8, (a0)
-; LMULMAX8-NEXT: vmset.m v0
; LMULMAX8-NEXT: fsrmi a1, 1
-; LMULMAX8-NEXT: vfcvt.f.xu.v v8, v8, v0.t
+; LMULMAX8-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX8-NEXT: fsrm a1
; LMULMAX8-NEXT: li a1, 52
; LMULMAX8-NEXT: vsrl.vx v8, v8, a1
; LMULMAX2-RV32F-NEXT: vle32.v v8, (a0)
; LMULMAX2-RV32F-NEXT: vrsub.vi v9, v8, 0
; LMULMAX2-RV32F-NEXT: vand.vv v9, v8, v9
-; LMULMAX2-RV32F-NEXT: vmset.m v0
; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
-; LMULMAX2-RV32F-NEXT: vfcvt.f.xu.v v9, v9, v0.t
+; LMULMAX2-RV32F-NEXT: vfcvt.f.xu.v v9, v9
; LMULMAX2-RV32F-NEXT: fsrm a1
; LMULMAX2-RV32F-NEXT: vsrl.vi v9, v9, 23
; LMULMAX2-RV32F-NEXT: li a1, 127
; LMULMAX2-RV64F-NEXT: vle32.v v8, (a0)
; LMULMAX2-RV64F-NEXT: vrsub.vi v9, v8, 0
; LMULMAX2-RV64F-NEXT: vand.vv v9, v8, v9
-; LMULMAX2-RV64F-NEXT: vmset.m v0
; LMULMAX2-RV64F-NEXT: fsrmi a1, 1
-; LMULMAX2-RV64F-NEXT: vfcvt.f.xu.v v9, v9, v0.t
+; LMULMAX2-RV64F-NEXT: vfcvt.f.xu.v v9, v9
; LMULMAX2-RV64F-NEXT: fsrm a1
; LMULMAX2-RV64F-NEXT: vsrl.vi v9, v9, 23
; LMULMAX2-RV64F-NEXT: li a1, 127
; LMULMAX2-RV32F-LABEL: cttz_v2i64:
; LMULMAX2-RV32F: # %bb.0:
; LMULMAX2-RV32F-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; LMULMAX2-RV32F-NEXT: vle64.v v9, (a0)
+; LMULMAX2-RV32F-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX2-RV32F-NEXT: vmv.v.i v10, 0
+; LMULMAX2-RV32F-NEXT: vmv.v.i v9, 0
; LMULMAX2-RV32F-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; LMULMAX2-RV32F-NEXT: vmseq.vv v8, v9, v10
-; LMULMAX2-RV32F-NEXT: vsub.vv v10, v10, v9
-; LMULMAX2-RV32F-NEXT: vand.vv v9, v9, v10
-; LMULMAX2-RV32F-NEXT: vmset.m v0
+; LMULMAX2-RV32F-NEXT: vmseq.vv v0, v8, v9
+; LMULMAX2-RV32F-NEXT: vsub.vv v9, v9, v8
+; LMULMAX2-RV32F-NEXT: vand.vv v8, v8, v9
; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v10, v9, v0.t
+; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v9, v8
; LMULMAX2-RV32F-NEXT: fsrm a1
-; LMULMAX2-RV32F-NEXT: vsrl.vi v9, v10, 23
+; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v9, 23
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
-; LMULMAX2-RV32F-NEXT: vzext.vf2 v10, v9
+; LMULMAX2-RV32F-NEXT: vzext.vf2 v9, v8
; LMULMAX2-RV32F-NEXT: li a1, 127
-; LMULMAX2-RV32F-NEXT: vsub.vx v9, v10, a1
+; LMULMAX2-RV32F-NEXT: vsub.vx v8, v9, a1
; LMULMAX2-RV32F-NEXT: li a1, 64
-; LMULMAX2-RV32F-NEXT: vmv.v.v v0, v8
-; LMULMAX2-RV32F-NEXT: vmerge.vxm v8, v9, a1, v0
+; LMULMAX2-RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
; LMULMAX2-RV32F-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32F-NEXT: ret
;
; LMULMAX2-RV64F-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64F-NEXT: vrsub.vi v9, v8, 0
; LMULMAX2-RV64F-NEXT: vand.vv v9, v8, v9
-; LMULMAX2-RV64F-NEXT: vmset.m v0
; LMULMAX2-RV64F-NEXT: fsrmi a1, 1
; LMULMAX2-RV64F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; LMULMAX2-RV64F-NEXT: vfncvt.f.xu.w v10, v9, v0.t
+; LMULMAX2-RV64F-NEXT: vfncvt.f.xu.w v10, v9
; LMULMAX2-RV64F-NEXT: fsrm a1
; LMULMAX2-RV64F-NEXT: vsrl.vi v9, v10, 23
; LMULMAX2-RV64F-NEXT: li a1, 127
; LMULMAX2-RV32D-LABEL: cttz_v2i64:
; LMULMAX2-RV32D: # %bb.0:
; LMULMAX2-RV32D-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; LMULMAX2-RV32D-NEXT: vle64.v v9, (a0)
+; LMULMAX2-RV32D-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32D-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX2-RV32D-NEXT: vmv.v.i v10, 0
+; LMULMAX2-RV32D-NEXT: vmv.v.i v9, 0
; LMULMAX2-RV32D-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; LMULMAX2-RV32D-NEXT: vmseq.vv v8, v9, v10
-; LMULMAX2-RV32D-NEXT: vsub.vv v10, v10, v9
-; LMULMAX2-RV32D-NEXT: vand.vv v9, v9, v10
-; LMULMAX2-RV32D-NEXT: vmset.m v0
+; LMULMAX2-RV32D-NEXT: vmseq.vv v0, v8, v9
+; LMULMAX2-RV32D-NEXT: vsub.vv v9, v9, v8
+; LMULMAX2-RV32D-NEXT: vand.vv v8, v8, v9
; LMULMAX2-RV32D-NEXT: fsrmi a1, 1
-; LMULMAX2-RV32D-NEXT: vfcvt.f.xu.v v9, v9, v0.t
+; LMULMAX2-RV32D-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX2-RV32D-NEXT: fsrm a1
; LMULMAX2-RV32D-NEXT: li a1, 52
-; LMULMAX2-RV32D-NEXT: vsrl.vx v9, v9, a1
+; LMULMAX2-RV32D-NEXT: vsrl.vx v8, v8, a1
; LMULMAX2-RV32D-NEXT: li a1, 1023
-; LMULMAX2-RV32D-NEXT: vsub.vx v9, v9, a1
+; LMULMAX2-RV32D-NEXT: vsub.vx v8, v8, a1
; LMULMAX2-RV32D-NEXT: li a1, 64
-; LMULMAX2-RV32D-NEXT: vmv.v.v v0, v8
-; LMULMAX2-RV32D-NEXT: vmerge.vxm v8, v9, a1, v0
+; LMULMAX2-RV32D-NEXT: vmerge.vxm v8, v8, a1, v0
; LMULMAX2-RV32D-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32D-NEXT: ret
;
; LMULMAX2-RV64D-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64D-NEXT: vrsub.vi v9, v8, 0
; LMULMAX2-RV64D-NEXT: vand.vv v9, v8, v9
-; LMULMAX2-RV64D-NEXT: vmset.m v0
; LMULMAX2-RV64D-NEXT: fsrmi a1, 1
-; LMULMAX2-RV64D-NEXT: vfcvt.f.xu.v v9, v9, v0.t
+; LMULMAX2-RV64D-NEXT: vfcvt.f.xu.v v9, v9
; LMULMAX2-RV64D-NEXT: fsrm a1
; LMULMAX2-RV64D-NEXT: li a1, 52
; LMULMAX2-RV64D-NEXT: vsrl.vx v9, v9, a1
; LMULMAX8-RV32-LABEL: cttz_v2i64:
; LMULMAX8-RV32: # %bb.0:
; LMULMAX8-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; LMULMAX8-RV32-NEXT: vle64.v v9, (a0)
+; LMULMAX8-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX8-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX8-RV32-NEXT: vmv.v.i v10, 0
+; LMULMAX8-RV32-NEXT: vmv.v.i v9, 0
; LMULMAX8-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; LMULMAX8-RV32-NEXT: vmseq.vv v8, v9, v10
-; LMULMAX8-RV32-NEXT: vsub.vv v10, v10, v9
-; LMULMAX8-RV32-NEXT: vand.vv v9, v9, v10
-; LMULMAX8-RV32-NEXT: vmset.m v0
+; LMULMAX8-RV32-NEXT: vmseq.vv v0, v8, v9
+; LMULMAX8-RV32-NEXT: vsub.vv v9, v9, v8
+; LMULMAX8-RV32-NEXT: vand.vv v8, v8, v9
; LMULMAX8-RV32-NEXT: fsrmi a1, 1
-; LMULMAX8-RV32-NEXT: vfcvt.f.xu.v v9, v9, v0.t
+; LMULMAX8-RV32-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX8-RV32-NEXT: fsrm a1
; LMULMAX8-RV32-NEXT: li a1, 52
-; LMULMAX8-RV32-NEXT: vsrl.vx v9, v9, a1
+; LMULMAX8-RV32-NEXT: vsrl.vx v8, v8, a1
; LMULMAX8-RV32-NEXT: li a1, 1023
-; LMULMAX8-RV32-NEXT: vsub.vx v9, v9, a1
+; LMULMAX8-RV32-NEXT: vsub.vx v8, v8, a1
; LMULMAX8-RV32-NEXT: li a1, 64
-; LMULMAX8-RV32-NEXT: vmv.v.v v0, v8
-; LMULMAX8-RV32-NEXT: vmerge.vxm v8, v9, a1, v0
+; LMULMAX8-RV32-NEXT: vmerge.vxm v8, v8, a1, v0
; LMULMAX8-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX8-RV32-NEXT: ret
;
; LMULMAX8-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX8-RV64-NEXT: vrsub.vi v9, v8, 0
; LMULMAX8-RV64-NEXT: vand.vv v9, v8, v9
-; LMULMAX8-RV64-NEXT: vmset.m v0
; LMULMAX8-RV64-NEXT: fsrmi a1, 1
-; LMULMAX8-RV64-NEXT: vfcvt.f.xu.v v9, v9, v0.t
+; LMULMAX8-RV64-NEXT: vfcvt.f.xu.v v9, v9
; LMULMAX8-RV64-NEXT: fsrm a1
; LMULMAX8-RV64-NEXT: li a1, 52
; LMULMAX8-RV64-NEXT: vsrl.vx v9, v9, a1
; LMULMAX2-RV32F-NEXT: vle32.v v8, (a0)
; LMULMAX2-RV32F-NEXT: vrsub.vi v10, v8, 0
; LMULMAX2-RV32F-NEXT: vand.vv v10, v8, v10
-; LMULMAX2-RV32F-NEXT: vmset.m v0
; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
-; LMULMAX2-RV32F-NEXT: vfcvt.f.xu.v v10, v10, v0.t
+; LMULMAX2-RV32F-NEXT: vfcvt.f.xu.v v10, v10
; LMULMAX2-RV32F-NEXT: fsrm a1
; LMULMAX2-RV32F-NEXT: vsrl.vi v10, v10, 23
; LMULMAX2-RV32F-NEXT: li a1, 127
; LMULMAX2-RV64F-NEXT: vle32.v v8, (a0)
; LMULMAX2-RV64F-NEXT: vrsub.vi v10, v8, 0
; LMULMAX2-RV64F-NEXT: vand.vv v10, v8, v10
-; LMULMAX2-RV64F-NEXT: vmset.m v0
; LMULMAX2-RV64F-NEXT: fsrmi a1, 1
-; LMULMAX2-RV64F-NEXT: vfcvt.f.xu.v v10, v10, v0.t
+; LMULMAX2-RV64F-NEXT: vfcvt.f.xu.v v10, v10
; LMULMAX2-RV64F-NEXT: fsrm a1
; LMULMAX2-RV64F-NEXT: vsrl.vi v10, v10, 23
; LMULMAX2-RV64F-NEXT: li a1, 127
; LMULMAX2-RV32D-NEXT: vle32.v v8, (a0)
; LMULMAX2-RV32D-NEXT: vrsub.vi v10, v8, 0
; LMULMAX2-RV32D-NEXT: vand.vv v10, v8, v10
-; LMULMAX2-RV32D-NEXT: vmset.m v0
; LMULMAX2-RV32D-NEXT: fsrmi a1, 1
-; LMULMAX2-RV32D-NEXT: vfcvt.f.xu.v v10, v10, v0.t
+; LMULMAX2-RV32D-NEXT: vfcvt.f.xu.v v10, v10
; LMULMAX2-RV32D-NEXT: fsrm a1
; LMULMAX2-RV32D-NEXT: vsrl.vi v10, v10, 23
; LMULMAX2-RV32D-NEXT: li a1, 127
; LMULMAX2-RV64D-NEXT: vle32.v v8, (a0)
; LMULMAX2-RV64D-NEXT: vrsub.vi v10, v8, 0
; LMULMAX2-RV64D-NEXT: vand.vv v10, v8, v10
-; LMULMAX2-RV64D-NEXT: vmset.m v0
; LMULMAX2-RV64D-NEXT: fsrmi a1, 1
-; LMULMAX2-RV64D-NEXT: vfcvt.f.xu.v v10, v10, v0.t
+; LMULMAX2-RV64D-NEXT: vfcvt.f.xu.v v10, v10
; LMULMAX2-RV64D-NEXT: fsrm a1
; LMULMAX2-RV64D-NEXT: vsrl.vi v10, v10, 23
; LMULMAX2-RV64D-NEXT: li a1, 127
; LMULMAX2-RV32F-LABEL: cttz_v4i64:
; LMULMAX2-RV32F: # %bb.0:
; LMULMAX2-RV32F-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; LMULMAX2-RV32F-NEXT: vle64.v v10, (a0)
+; LMULMAX2-RV32F-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32F-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; LMULMAX2-RV32F-NEXT: vmv.v.i v12, 0
+; LMULMAX2-RV32F-NEXT: vmv.v.i v10, 0
; LMULMAX2-RV32F-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; LMULMAX2-RV32F-NEXT: vmseq.vv v8, v10, v12
-; LMULMAX2-RV32F-NEXT: vsub.vv v12, v12, v10
-; LMULMAX2-RV32F-NEXT: vand.vv v10, v10, v12
-; LMULMAX2-RV32F-NEXT: vmset.m v0
+; LMULMAX2-RV32F-NEXT: vmseq.vv v0, v8, v10
+; LMULMAX2-RV32F-NEXT: vsub.vv v10, v10, v8
+; LMULMAX2-RV32F-NEXT: vand.vv v8, v8, v10
; LMULMAX2-RV32F-NEXT: fsrmi a1, 1
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v9, v10, v0.t
+; LMULMAX2-RV32F-NEXT: vfncvt.f.xu.w v10, v8
; LMULMAX2-RV32F-NEXT: fsrm a1
-; LMULMAX2-RV32F-NEXT: vsrl.vi v9, v9, 23
+; LMULMAX2-RV32F-NEXT: vsrl.vi v8, v10, 23
; LMULMAX2-RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; LMULMAX2-RV32F-NEXT: vzext.vf2 v10, v9
+; LMULMAX2-RV32F-NEXT: vzext.vf2 v10, v8
; LMULMAX2-RV32F-NEXT: li a1, 127
-; LMULMAX2-RV32F-NEXT: vsub.vx v10, v10, a1
+; LMULMAX2-RV32F-NEXT: vsub.vx v8, v10, a1
; LMULMAX2-RV32F-NEXT: li a1, 64
-; LMULMAX2-RV32F-NEXT: vmv1r.v v0, v8
-; LMULMAX2-RV32F-NEXT: vmerge.vxm v8, v10, a1, v0
+; LMULMAX2-RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
; LMULMAX2-RV32F-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32F-NEXT: ret
;
; LMULMAX2-RV64F-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64F-NEXT: vrsub.vi v10, v8, 0
; LMULMAX2-RV64F-NEXT: vand.vv v10, v8, v10
-; LMULMAX2-RV64F-NEXT: vmset.m v0
; LMULMAX2-RV64F-NEXT: fsrmi a1, 1
; LMULMAX2-RV64F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; LMULMAX2-RV64F-NEXT: vfncvt.f.xu.w v12, v10, v0.t
+; LMULMAX2-RV64F-NEXT: vfncvt.f.xu.w v12, v10
; LMULMAX2-RV64F-NEXT: fsrm a1
; LMULMAX2-RV64F-NEXT: vsrl.vi v10, v12, 23
; LMULMAX2-RV64F-NEXT: li a1, 127
; LMULMAX2-RV32D-LABEL: cttz_v4i64:
; LMULMAX2-RV32D: # %bb.0:
; LMULMAX2-RV32D-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; LMULMAX2-RV32D-NEXT: vle64.v v10, (a0)
+; LMULMAX2-RV32D-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV32D-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; LMULMAX2-RV32D-NEXT: vmv.v.i v12, 0
+; LMULMAX2-RV32D-NEXT: vmv.v.i v10, 0
; LMULMAX2-RV32D-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; LMULMAX2-RV32D-NEXT: vmseq.vv v8, v10, v12
-; LMULMAX2-RV32D-NEXT: vsub.vv v12, v12, v10
-; LMULMAX2-RV32D-NEXT: vand.vv v10, v10, v12
-; LMULMAX2-RV32D-NEXT: vmset.m v0
+; LMULMAX2-RV32D-NEXT: vmseq.vv v0, v8, v10
+; LMULMAX2-RV32D-NEXT: vsub.vv v10, v10, v8
+; LMULMAX2-RV32D-NEXT: vand.vv v8, v8, v10
; LMULMAX2-RV32D-NEXT: fsrmi a1, 1
-; LMULMAX2-RV32D-NEXT: vfcvt.f.xu.v v10, v10, v0.t
+; LMULMAX2-RV32D-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX2-RV32D-NEXT: fsrm a1
; LMULMAX2-RV32D-NEXT: li a1, 52
-; LMULMAX2-RV32D-NEXT: vsrl.vx v10, v10, a1
+; LMULMAX2-RV32D-NEXT: vsrl.vx v8, v8, a1
; LMULMAX2-RV32D-NEXT: li a1, 1023
-; LMULMAX2-RV32D-NEXT: vsub.vx v10, v10, a1
+; LMULMAX2-RV32D-NEXT: vsub.vx v8, v8, a1
; LMULMAX2-RV32D-NEXT: li a1, 64
-; LMULMAX2-RV32D-NEXT: vmv1r.v v0, v8
-; LMULMAX2-RV32D-NEXT: vmerge.vxm v8, v10, a1, v0
+; LMULMAX2-RV32D-NEXT: vmerge.vxm v8, v8, a1, v0
; LMULMAX2-RV32D-NEXT: vse64.v v8, (a0)
; LMULMAX2-RV32D-NEXT: ret
;
; LMULMAX2-RV64D-NEXT: vle64.v v8, (a0)
; LMULMAX2-RV64D-NEXT: vrsub.vi v10, v8, 0
; LMULMAX2-RV64D-NEXT: vand.vv v10, v8, v10
-; LMULMAX2-RV64D-NEXT: vmset.m v0
; LMULMAX2-RV64D-NEXT: fsrmi a1, 1
-; LMULMAX2-RV64D-NEXT: vfcvt.f.xu.v v10, v10, v0.t
+; LMULMAX2-RV64D-NEXT: vfcvt.f.xu.v v10, v10
; LMULMAX2-RV64D-NEXT: fsrm a1
; LMULMAX2-RV64D-NEXT: li a1, 52
; LMULMAX2-RV64D-NEXT: vsrl.vx v10, v10, a1
; LMULMAX8-RV32-LABEL: cttz_v4i64:
; LMULMAX8-RV32: # %bb.0:
; LMULMAX8-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; LMULMAX8-RV32-NEXT: vle64.v v10, (a0)
+; LMULMAX8-RV32-NEXT: vle64.v v8, (a0)
; LMULMAX8-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
-; LMULMAX8-RV32-NEXT: vmv.v.i v12, 0
+; LMULMAX8-RV32-NEXT: vmv.v.i v10, 0
; LMULMAX8-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; LMULMAX8-RV32-NEXT: vmseq.vv v8, v10, v12
-; LMULMAX8-RV32-NEXT: vsub.vv v12, v12, v10
-; LMULMAX8-RV32-NEXT: vand.vv v10, v10, v12
-; LMULMAX8-RV32-NEXT: vmset.m v0
+; LMULMAX8-RV32-NEXT: vmseq.vv v0, v8, v10
+; LMULMAX8-RV32-NEXT: vsub.vv v10, v10, v8
+; LMULMAX8-RV32-NEXT: vand.vv v8, v8, v10
; LMULMAX8-RV32-NEXT: fsrmi a1, 1
-; LMULMAX8-RV32-NEXT: vfcvt.f.xu.v v10, v10, v0.t
+; LMULMAX8-RV32-NEXT: vfcvt.f.xu.v v8, v8
; LMULMAX8-RV32-NEXT: fsrm a1
; LMULMAX8-RV32-NEXT: li a1, 52
-; LMULMAX8-RV32-NEXT: vsrl.vx v10, v10, a1
+; LMULMAX8-RV32-NEXT: vsrl.vx v8, v8, a1
; LMULMAX8-RV32-NEXT: li a1, 1023
-; LMULMAX8-RV32-NEXT: vsub.vx v10, v10, a1
+; LMULMAX8-RV32-NEXT: vsub.vx v8, v8, a1
; LMULMAX8-RV32-NEXT: li a1, 64
-; LMULMAX8-RV32-NEXT: vmv1r.v v0, v8
-; LMULMAX8-RV32-NEXT: vmerge.vxm v8, v10, a1, v0
+; LMULMAX8-RV32-NEXT: vmerge.vxm v8, v8, a1, v0
; LMULMAX8-RV32-NEXT: vse64.v v8, (a0)
; LMULMAX8-RV32-NEXT: ret
;
; LMULMAX8-RV64-NEXT: vle64.v v8, (a0)
; LMULMAX8-RV64-NEXT: vrsub.vi v10, v8, 0
; LMULMAX8-RV64-NEXT: vand.vv v10, v8, v10
-; LMULMAX8-RV64-NEXT: vmset.m v0
; LMULMAX8-RV64-NEXT: fsrmi a1, 1
-; LMULMAX8-RV64-NEXT: vfcvt.f.xu.v v10, v10, v0.t
+; LMULMAX8-RV64-NEXT: vfcvt.f.xu.v v10, v10
; LMULMAX8-RV64-NEXT: fsrm a1
; LMULMAX8-RV64-NEXT: li a1, 52
; LMULMAX8-RV64-NEXT: vsrl.vx v10, v10, a1
define <vscale x 1 x i16> @ceil_nxv1f32_to_si16(<vscale x 1 x float> %x) {
; RV32-LABEL: ceil_nxv1f32_to_si16:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfncvt.x.f.w v9, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; RV32-NEXT: vfncvt.x.f.w v9, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv1f32_to_si16:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfncvt.x.f.w v9, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; RV64-NEXT: vfncvt.x.f.w v9, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
define <vscale x 1 x i16> @ceil_nxv1f32_to_ui16(<vscale x 1 x float> %x) {
; RV32-LABEL: ceil_nxv1f32_to_ui16:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfncvt.xu.f.w v9, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; RV32-NEXT: vfncvt.xu.f.w v9, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv1f32_to_ui16:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfncvt.xu.f.w v9, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; RV64-NEXT: vfncvt.xu.f.w v9, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
define <vscale x 1 x i32> @ceil_nxv1f32_to_si32(<vscale x 1 x float> %x) {
; RV32-LABEL: ceil_nxv1f32_to_si32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv1f32_to_si32:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; RV64-NEXT: vfcvt.x.f.v v8, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: ret
%a = call <vscale x 1 x float> @llvm.ceil.nxv1f32(<vscale x 1 x float> %x)
define <vscale x 1 x i32> @ceil_nxv1f32_to_ui32(<vscale x 1 x float> %x) {
; RV32-LABEL: ceil_nxv1f32_to_ui32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfcvt.xu.f.v v8, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; RV32-NEXT: vfcvt.xu.f.v v8, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv1f32_to_ui32:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfcvt.xu.f.v v8, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; RV64-NEXT: vfcvt.xu.f.v v8, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: ret
%a = call <vscale x 1 x float> @llvm.ceil.nxv1f32(<vscale x 1 x float> %x)
define <vscale x 1 x i64> @ceil_nxv1f32_to_si64(<vscale x 1 x float> %x) {
; RV32-LABEL: ceil_nxv1f32_to_si64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfwcvt.x.f.v v9, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; RV32-NEXT: vfwcvt.x.f.v v9, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv1f32_to_si64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfwcvt.x.f.v v9, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; RV64-NEXT: vfwcvt.x.f.v v9, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
define <vscale x 1 x i64> @ceil_nxv1f32_to_ui64(<vscale x 1 x float> %x) {
; RV32-LABEL: ceil_nxv1f32_to_ui64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfwcvt.xu.f.v v9, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; RV32-NEXT: vfwcvt.xu.f.v v9, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv1f32_to_ui64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfwcvt.xu.f.v v9, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; RV64-NEXT: vfwcvt.xu.f.v v9, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
define <vscale x 4 x i16> @ceil_nxv4f32_to_si16(<vscale x 4 x float> %x) {
; RV32-LABEL: ceil_nxv4f32_to_si16:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfncvt.x.f.w v10, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; RV32-NEXT: vfncvt.x.f.w v10, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: vmv.v.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv4f32_to_si16:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfncvt.x.f.w v10, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; RV64-NEXT: vfncvt.x.f.w v10, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: vmv.v.v v8, v10
; RV64-NEXT: ret
define <vscale x 4 x i16> @ceil_nxv4f32_to_ui16(<vscale x 4 x float> %x) {
; RV32-LABEL: ceil_nxv4f32_to_ui16:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfncvt.xu.f.w v10, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; RV32-NEXT: vfncvt.xu.f.w v10, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: vmv.v.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv4f32_to_ui16:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfncvt.xu.f.w v10, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; RV64-NEXT: vfncvt.xu.f.w v10, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: vmv.v.v v8, v10
; RV64-NEXT: ret
define <vscale x 4 x i32> @ceil_nxv4f32_to_si32(<vscale x 4 x float> %x) {
; RV32-LABEL: ceil_nxv4f32_to_si32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv4f32_to_si32:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; RV64-NEXT: vfcvt.x.f.v v8, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: ret
%a = call <vscale x 4 x float> @llvm.ceil.nxv4f32(<vscale x 4 x float> %x)
define <vscale x 4 x i32> @ceil_nxv4f32_to_ui32(<vscale x 4 x float> %x) {
; RV32-LABEL: ceil_nxv4f32_to_ui32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfcvt.xu.f.v v8, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; RV32-NEXT: vfcvt.xu.f.v v8, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv4f32_to_ui32:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfcvt.xu.f.v v8, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; RV64-NEXT: vfcvt.xu.f.v v8, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: ret
%a = call <vscale x 4 x float> @llvm.ceil.nxv4f32(<vscale x 4 x float> %x)
define <vscale x 4 x i64> @ceil_nxv4f32_to_si64(<vscale x 4 x float> %x) {
; RV32-LABEL: ceil_nxv4f32_to_si64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfwcvt.x.f.v v12, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; RV32-NEXT: vfwcvt.x.f.v v12, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv4f32_to_si64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfwcvt.x.f.v v12, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; RV64-NEXT: vfwcvt.x.f.v v12, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
define <vscale x 4 x i64> @ceil_nxv4f32_to_ui64(<vscale x 4 x float> %x) {
; RV32-LABEL: ceil_nxv4f32_to_ui64:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfwcvt.xu.f.v v12, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; RV32-NEXT: vfwcvt.xu.f.v v12, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: vmv4r.v v8, v12
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv4f32_to_ui64:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfwcvt.xu.f.v v12, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; RV64-NEXT: vfwcvt.xu.f.v v12, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: vmv4r.v v8, v12
; RV64-NEXT: ret
define <vscale x 1 x i8> @ceil_nxv1f16_to_si8(<vscale x 1 x half> %x) {
; RV32-LABEL: ceil_nxv1f16_to_si8:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfncvt.x.f.w v9, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; RV32-NEXT: vfncvt.x.f.w v9, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv1f16_to_si8:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfncvt.x.f.w v9, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; RV64-NEXT: vfncvt.x.f.w v9, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
define <vscale x 1 x i8> @ceil_nxv1f16_to_ui8(<vscale x 1 x half> %x) {
; RV32-LABEL: ceil_nxv1f16_to_ui8:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfncvt.xu.f.w v9, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; RV32-NEXT: vfncvt.xu.f.w v9, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv1f16_to_ui8:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfncvt.xu.f.w v9, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
+; RV64-NEXT: vfncvt.xu.f.w v9, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
define <vscale x 1 x i16> @ceil_nxv1f16_to_si16(<vscale x 1 x half> %x) {
; RV32-LABEL: ceil_nxv1f16_to_si16:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv1f16_to_si16:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; RV64-NEXT: vfcvt.x.f.v v8, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: ret
%a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)
define <vscale x 1 x i16> @ceil_nxv1f16_to_ui16(<vscale x 1 x half> %x) {
; RV32-LABEL: ceil_nxv1f16_to_ui16:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfcvt.xu.f.v v8, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; RV32-NEXT: vfcvt.xu.f.v v8, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv1f16_to_ui16:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfcvt.xu.f.v v8, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; RV64-NEXT: vfcvt.xu.f.v v8, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: ret
%a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)
define <vscale x 1 x i32> @ceil_nxv1f16_to_si32(<vscale x 1 x half> %x) {
; RV32-LABEL: ceil_nxv1f16_to_si32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfwcvt.x.f.v v9, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; RV32-NEXT: vfwcvt.x.f.v v9, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv1f16_to_si32:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfwcvt.x.f.v v9, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; RV64-NEXT: vfwcvt.x.f.v v9, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
define <vscale x 1 x i32> @ceil_nxv1f16_to_ui32(<vscale x 1 x half> %x) {
; RV32-LABEL: ceil_nxv1f16_to_ui32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfwcvt.xu.f.v v9, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; RV32-NEXT: vfwcvt.xu.f.v v9, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv1f16_to_ui32:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfwcvt.xu.f.v v9, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
+; RV64-NEXT: vfwcvt.xu.f.v v9, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
define <vscale x 4 x i8> @ceil_nxv4f16_to_si8(<vscale x 4 x half> %x) {
; RV32-LABEL: ceil_nxv4f16_to_si8:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfncvt.x.f.w v9, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; RV32-NEXT: vfncvt.x.f.w v9, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv4f16_to_si8:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfncvt.x.f.w v9, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; RV64-NEXT: vfncvt.x.f.w v9, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
define <vscale x 4 x i8> @ceil_nxv4f16_to_ui8(<vscale x 4 x half> %x) {
; RV32-LABEL: ceil_nxv4f16_to_ui8:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfncvt.xu.f.w v9, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; RV32-NEXT: vfncvt.xu.f.w v9, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv4f16_to_ui8:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfncvt.xu.f.w v9, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
+; RV64-NEXT: vfncvt.xu.f.w v9, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: vmv1r.v v8, v9
; RV64-NEXT: ret
define <vscale x 4 x i16> @ceil_nxv4f16_to_si16(<vscale x 4 x half> %x) {
; RV32-LABEL: ceil_nxv4f16_to_si16:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; RV32-NEXT: vfcvt.x.f.v v8, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv4f16_to_si16:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfcvt.x.f.v v8, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; RV64-NEXT: vfcvt.x.f.v v8, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: ret
%a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)
define <vscale x 4 x i16> @ceil_nxv4f16_to_ui16(<vscale x 4 x half> %x) {
; RV32-LABEL: ceil_nxv4f16_to_ui16:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfcvt.xu.f.v v8, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; RV32-NEXT: vfcvt.xu.f.v v8, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv4f16_to_ui16:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfcvt.xu.f.v v8, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; RV64-NEXT: vfcvt.xu.f.v v8, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: ret
%a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)
define <vscale x 4 x i32> @ceil_nxv4f16_to_si32(<vscale x 4 x half> %x) {
; RV32-LABEL: ceil_nxv4f16_to_si32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfwcvt.x.f.v v10, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; RV32-NEXT: vfwcvt.x.f.v v10, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv4f16_to_si32:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfwcvt.x.f.v v10, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; RV64-NEXT: vfwcvt.x.f.v v10, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret
define <vscale x 4 x i32> @ceil_nxv4f16_to_ui32(<vscale x 4 x half> %x) {
; RV32-LABEL: ceil_nxv4f16_to_ui32:
; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV32-NEXT: vmset.m v0
; RV32-NEXT: fsrmi a0, 3
-; RV32-NEXT: vfwcvt.xu.f.v v10, v8, v0.t
+; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; RV32-NEXT: vfwcvt.xu.f.v v10, v8
; RV32-NEXT: fsrm a0
; RV32-NEXT: vmv2r.v v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: ceil_nxv4f16_to_ui32:
; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; RV64-NEXT: vmset.m v0
; RV64-NEXT: fsrmi a0, 3
-; RV64-NEXT: vfwcvt.xu.f.v v10, v8, v0.t
+; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, ma
+; RV64-NEXT: vfwcvt.xu.f.v v10, v8
; RV64-NEXT: fsrm a0
; RV64-NEXT: vmv2r.v v8, v10
; RV64-NEXT: ret