register_bank = context.get("register_bank")
self.assertTrue(register_bank[0] != 'E')
+ self.test_sequence.add_log_lines(
+ ["read packet: $G" + register_bank + "#00",
+ {"direction": "send", "regex": r"^\$(.+)#[0-9a-fA-F]{2}$",
+ "capture": {1: "G_reply"}}],
+ True)
+ context = self.expect_gdbremote_sequence()
+ self.assertTrue(context.get("G_reply")[0] != 'E')
+
+
@skipIfOutOfTreeDebugserver
@debugserver_test
def test_g_packet_debugserver(self):
// Copy fcw through mxcsrmask as there is no padding
memcpy(&m_state.context.fpu.no_avx.__fpu_fcw, p, 5);
- p += 5;
+ // We wrote 5 bytes, but we skip 6 to account for __fpu_rsrv1
+ // to match the g_fpu_registers_* tables.
+ p += 6;
memcpy(&m_state.context.fpu.no_avx.__fpu_fop, p, 8);
p += 8;
memcpy(&m_state.context.fpu.no_avx.__fpu_dp, p, 6);