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arm64: dts: imx8mm-beacon-som: Fix whitespace issue
authorAdam Ford <aford173@gmail.com>
Sat, 31 Oct 2020 12:31:14 +0000 (07:31 -0500)
committerShawn Guo <shawnguo@kernel.org>
Mon, 30 Nov 2020 14:30:29 +0000 (22:30 +0800)
The pinmux subnodes are indented too much.  This patch does nothing
more than remove an extra tab.  There are no functional changes.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi patch | blob | history

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
index c74e006..6b53830 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
@@ -284,166 +284,166 @@
 };
 
 &iomuxc {
-               pinctrl_fec1: fec1grp {
-                       fsl,pins = <
-                               MX8MM_IOMUXC_ENET_MDC_ENET1_MDC         0x3
-                               MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO       0x3
-                               MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3   0x1f
-                               MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2   0x1f
-                               MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1   0x1f
-                               MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0   0x1f
-                               MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3   0x91
-                               MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2   0x91
-                               MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1   0x91
-                               MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0   0x91
-                               MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC   0x1f
-                               MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC   0x91
-                               MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
-                               MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
-                               MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22        0x19
-                       >;
-               };
+       pinctrl_fec1: fec1grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_ENET_MDC_ENET1_MDC         0x3
+                       MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO       0x3
+                       MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3   0x1f
+                       MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2   0x1f
+                       MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1   0x1f
+                       MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0   0x1f
+                       MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3   0x91
+                       MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2   0x91
+                       MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1   0x91
+                       MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0   0x91
+                       MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC   0x1f
+                       MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC   0x91
+                       MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
+                       MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
+                       MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22        0x19
+               >;
+       };
 
-               pinctrl_i2c1: i2c1grp {
-                       fsl,pins = <
-                               MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
-                               MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
-                       >;
-               };
+       pinctrl_i2c1: i2c1grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
+                       MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
+               >;
+       };
 
-               pinctrl_i2c3: i2c3grp {
-                       fsl,pins = <
-                               MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
-                               MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
-                       >;
-               };
+       pinctrl_i2c3: i2c3grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
+                       MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
+               >;
+       };
 
-               pinctrl_flexspi: flexspigrp {
-                       fsl,pins = <
-                               MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
-                               MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
-                               MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
-                               MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
-                               MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
-                               MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
-                       >;
-               };
+       pinctrl_flexspi: flexspigrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
+                       MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
+                       MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
+                       MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
+                       MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
+                       MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
+               >;
+       };
 
-               pinctrl_pmic: pmicirqgrp {
-                       fsl,pins = <
-                               MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3       0x141
-                       >;
-               };
+       pinctrl_pmic: pmicirqgrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3       0x141
+               >;
+       };
 
-               pinctrl_uart1: uart1grp {
-                       fsl,pins = <
-                               MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140
-                               MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140
-                               MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B  0x140
-                               MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B  0x140
-                               MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6        0x19
-                               MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7        0x19
-                               MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8        0x19
-                               MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K      0x141
-                       >;
-               };
+       pinctrl_uart1: uart1grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140
+                       MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140
+                       MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B  0x140
+                       MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B  0x140
+                       MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6        0x19
+                       MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7        0x19
+                       MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8        0x19
+                       MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K      0x141
+               >;
+       };
 
-               pinctrl_usdhc1_gpio: usdhc1gpiogrp {
-                       fsl,pins = <
-                               MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10     0x41
-                       >;
-               };
+       pinctrl_usdhc1_gpio: usdhc1gpiogrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10     0x41
+               >;
+       };
 
-               pinctrl_usdhc1: usdhc1grp {
-                       fsl,pins = <
-                               MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x190
-                               MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d0
-                               MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d0
-                               MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d0
-                               MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d0
-                               MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d0
-                       >;
-               };
+       pinctrl_usdhc1: usdhc1grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x190
+                       MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d0
+                       MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d0
+                       MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d0
+                       MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d0
+                       MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d0
+               >;
+       };
 
-               pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
-                       fsl,pins = <
-                               MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x194
-                               MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d4
-                               MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d4
-                               MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d4
-                               MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d4
-                               MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d4
-                       >;
-               };
+       pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x194
+                       MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d4
+                       MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d4
+                       MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d4
+                       MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d4
+                       MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d4
+               >;
+       };
 
-               pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
-                       fsl,pins = <
-                               MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x196
-                               MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d6
-                               MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d6
-                               MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d6
-                               MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d6
-                               MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d6
-                       >;
-               };
+       pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x196
+                       MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d6
+                       MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d6
+                       MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d6
+                       MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d6
+                       MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d6
+               >;
+       };
 
-               pinctrl_usdhc3: usdhc3grp {
-                       fsl,pins = <
-                               MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x190
-                               MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
-                               MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
-                               MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
-                               MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
-                               MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
-                               MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
-                               MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
-                               MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
-                               MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
-                               MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
-                       >;
-               };
+       pinctrl_usdhc3: usdhc3grp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x190
+                       MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
+                       MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
+                       MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
+                       MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
+                       MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
+                       MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
+                       MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
+                       MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
+                       MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
+                       MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
+               >;
+       };
 
-               pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
-                       fsl,pins = <
-                               MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x194
-                               MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
-                               MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
-                               MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
-                               MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
-                               MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
-                               MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
-                               MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
-                               MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
-                               MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
-                               MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
-                       >;
-               };
+       pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x194
+                       MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
+                       MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
+                       MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
+                       MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
+                       MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
+                       MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
+                       MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
+                       MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
+                       MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
+                       MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
+               >;
+       };
 
-               pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
-                       fsl,pins = <
-                               MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x196
-                               MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
-                               MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
-                               MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
-                               MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
-                               MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
-                               MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
-                               MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
-                               MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
-                               MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
-                               MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
-                       >;
-               };
+       pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x196
+                       MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
+                       MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
+                       MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
+                       MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
+                       MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
+                       MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
+                       MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
+                       MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
+                       MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
+                       MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
+               >;
+       };
 
-               pinctrl_wdog: wdoggrp {
-                       fsl,pins = <
-                               MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0x166
-                       >;
-               };
+       pinctrl_wdog: wdoggrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0x166
+               >;
+       };
 
-               pinctrl_wlan: wlangrp {
-                       fsl,pins = <
-                               MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9                0x111
-                       >;
-               };
+       pinctrl_wlan: wlangrp {
+               fsl,pins = <
+                       MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9                0x111
+               >;
+       };
 };
Domain: System / Kernel;