arm64: dts: mt8183: add MediaTek MDP3 nodes

Add device nodes for Media Data Path 3 (MDP3) modules.

Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220823023803.27850-4-moudy.ho@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 9d32871..1543876 100644 (file)
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1691,6 +1691,60 @@
                        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
                };
 
+               mdp3-rdma0@14001000 {
+                       compatible = "mediatek,mt8183-mdp3-rdma";
+                       reg = <0 0x14001000 0 0x1000>;
+                       mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
+                       mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
+                                             <CMDQ_EVENT_MDP_RDMA0_EOF>;
+                       power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+                       clocks = <&mmsys CLK_MM_MDP_RDMA0>,
+                                <&mmsys CLK_MM_MDP_RSZ1>;
+                       iommus = <&iommu M4U_PORT_MDP_RDMA0>;
+                       mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
+                                <&gce 21 CMDQ_THR_PRIO_LOWEST 0>;
+               };
+
+               mdp3-rsz0@14003000 {
+                       compatible = "mediatek,mt8183-mdp3-rsz";
+                       reg = <0 0x14003000 0 0x1000>;
+                       mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
+                       mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>,
+                                             <CMDQ_EVENT_MDP_RSZ0_EOF>;
+                       clocks = <&mmsys CLK_MM_MDP_RSZ0>;
+               };
+
+               mdp3-rsz1@14004000 {
+                       compatible = "mediatek,mt8183-mdp3-rsz";
+                       reg = <0 0x14004000 0 0x1000>;
+                       mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
+                       mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>,
+                                             <CMDQ_EVENT_MDP_RSZ1_EOF>;
+                       clocks = <&mmsys CLK_MM_MDP_RSZ1>;
+               };
+
+               mdp3-wrot0@14005000 {
+                       compatible = "mediatek,mt8183-mdp3-wrot";
+                       reg = <0 0x14005000 0 0x1000>;
+                       mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+                       mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
+                                             <CMDQ_EVENT_MDP_WROT0_EOF>;
+                       power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+                       clocks = <&mmsys CLK_MM_MDP_WROT0>;
+                       iommus = <&iommu M4U_PORT_MDP_WROT0>;
+               };
+
+               mdp3-wdma@14006000 {
+                       compatible = "mediatek,mt8183-mdp3-wdma";
+                       reg = <0 0x14006000 0 0x1000>;
+                       mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+                       mediatek,gce-events = <CMDQ_EVENT_MDP_WDMA0_SOF>,
+                                             <CMDQ_EVENT_MDP_WDMA0_EOF>;
+                       power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+                       clocks = <&mmsys CLK_MM_MDP_WDMA0>;
+                       iommus = <&iommu M4U_PORT_MDP_WDMA0>;
+               };
+
                ovl0: ovl@14008000 {
                        compatible = "mediatek,mt8183-disp-ovl";
                        reg = <0 0x14008000 0 0x1000>;
@@ -1834,6 +1888,15 @@
                        power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
                };
 
+               mdp3-ccorr@1401c000 {
+                       compatible = "mediatek,mt8183-mdp3-ccorr";
+                       reg = <0 0x1401c000 0 0x1000>;
+                       mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
+                       mediatek,gce-events = <CMDQ_EVENT_MDP_CCORR_SOF>,
+                                             <CMDQ_EVENT_MDP_CCORR_EOF>;
+                       clocks = <&mmsys CLK_MM_MDP_CCORR>;
+               };
+
                imgsys: syscon@15020000 {
                        compatible = "mediatek,mt8183-imgsys", "syscon";
                        reg = <0 0x15020000 0 0x1000>;